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Change subject: mb/google/nissa/var/riven: Update GPIO pins for 3rd dmic support
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Patch Set 2: Code-Review+2
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Change subject: mb/google/nissa/var/riven: Disable CNVi WIFI and BT based on fw_config
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/riven/fw_config.c:
https://review.coreboot.org/c/coreboot/+/83720/comment/6e4b7946_2fabdf23?us… :
PS1, Line 70: if (!fw_config_probe(FW_CONFIG(WIFI_TYPE, WIFI_CNVI))) {
> It will cause boot fail with "ASSERTION ERROR:file `src/soc/intel/alderlake/fsp_params.c`, line 820", seem like CB:83148.
> When fw_config is unprovisioned (CNVi WIFI is disabled), CNVi BT must be turned off. Thanks.
What if FW config doesn't exist and we are coming here to probe?
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Change subject: soc/intel/{adl,mtl}: Don't set up SPD on LPDDRx
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/84205/comment/903d52a0_68d72262?us… :
PS3, Line 239: = {};
Maybe use a ```memset``` instead of ```{}``` for default value initialization ?
- I don't see anywhere else in the code initializing structs default like this.
- since you have now kept the func ```mem_populate_channel_data``` under a condition ( the function was defaulting this variable to zero ), a memset here might be better IMO.
this is just a suggestion, ignore it if you think it will break the logic.
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Jon Murphy has submitted this change. ( https://review.coreboot.org/c/blobs/+/84181?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries
......................................................................
3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries
This PSP verstage is compatible with verified boot.
* FW Version: 15874.0.0
* PSP Version: 0.11.11.75
BUG=b:338615043
BRANCH=None
TEST=Build Dewatt BIOS image and boot to OS. Ensure that the PSP boots
in production mode.
Change-Id: Ida220410a4b896b746dda74258fa45a51524dbc2
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M mainboard/google/guybrush/dewatt_psp_verstage.signed.bin
M mainboard/google/guybrush/guybrush_psp_verstage.signed.bin
M mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin
3 files changed, 0 insertions(+), 0 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, approved
Jon Murphy: Verified
Rob Barnes: Looks good to me, approved
diff --git a/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin b/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin
index a2b5bc0..ef2be8f 100644
--- a/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin
+++ b/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin
Binary files differ
diff --git a/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin b/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin
index ccdf85a..8653223 100644
--- a/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin
+++ b/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin
Binary files differ
diff --git a/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin b/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin
index 28468f7..784ed67 100644
--- a/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin
+++ b/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin
Binary files differ
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(
2 is the latest approved patch-set.
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)Change subject: 3rdparty/blobs/mb/google/zork: Update PSP signing token
......................................................................
3rdparty/blobs/mb/google/zork: Update PSP signing token
The new signing token allows signing using signing infrastructure that
aligns with more recent AMD programs.
BUG=b:310651124
BRANCH=None
TEST=Build Vilboz BIOS Image and boot to OS. Ensure that PSP boots in
Production mode.
Change-Id: Idb11284cf4ef3abcfdd9186d672b995d82c35ad1
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M mainboard/google/zork/PCO_psp_verstagebl_fw_signing.stkn
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Rob Barnes: Looks good to me, approved
Jon Murphy: Verified
Karthik Ramasubramanian: Looks good to me, approved
Matt DeVillier: Looks good to me, approved
diff --git a/mainboard/google/zork/PCO_psp_verstagebl_fw_signing.stkn b/mainboard/google/zork/PCO_psp_verstagebl_fw_signing.stkn
index 15596f2..5a856bb 100644
--- a/mainboard/google/zork/PCO_psp_verstagebl_fw_signing.stkn
+++ b/mainboard/google/zork/PCO_psp_verstagebl_fw_signing.stkn
Binary files differ
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Change subject: mb/google/nissa/var/riven: Disable CNVi WIFI and BT based on fw_config
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Patch Set 1: Code-Review+2
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Change subject: mb/google/nissa/var/riven: Disable CNVi WIFI and BT based on fw_config
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Change subject: Cezanne: Add an option to enable A/B recovery scheme
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84195/comment/a8889f51_4dd2aedb?us… :
PS1, Line 9: Non A/B recovery
> This would simply be no recovery method, right? (Although vboot is an alternative methodology. […]
Done
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/84195/comment/8effe557_325ad0c5?us… :
PS1, Line 412: "Recovery A/B"
> maybe "Use A/B Recovery scheme"?
Done
https://review.coreboot.org/c/coreboot/+/84195/comment/0543d713_bf653c14?us… :
PS1, Line 415: Recovery A/B
> How about "Enable the PSP A/B Recovery mechanism"? Also, should we put some words in here about vbo […]
I dont know much about vboot's role in A/B recovery.
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Change subject: [WIP] superio/ite: Add support for IT8625E
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
IT8625E is an Embedded Controller. It should run its own FW from a separate flash. In such cases the EC FW programs the LDNs on init, so the serial port should be up at reset vector, without any help from coreboot side.
Also this chip will definitely not have a floppy LDN.
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