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Change subject: payloads/depthcharge: Add default 64-bit libpayload config
......................................................................
Patch Set 8:
(1 comment)
File payloads/libpayload/configs/defconfig_64:
https://review.coreboot.org/c/coreboot/+/84107/comment/214d235a_b68dc756?us… :
PS8, Line 1: # NOTE: remove to test _LP64 issue: CONFIG_LP_ARCH_X86_64=y
What is that first line ?
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Hello Bora Guvendik, Sowmya Aralguppe, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83946?usp=email
to look at the new patch set (#13).
The following approvals got outdated and were removed:
Code-Review+1 by Bora Guvendik, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
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soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
On Alder Lake, Meteor Lake and Panther Lake platforms the way size to
consider for NEM+ computation is the effective way size.
On Alder Lake, the External Design Specification #627270 "3.5.2
No-Eviction Mode (NEM) Sizes" provides a way to compute the effective
way size by reading the number of CBO. Unfortunately, reading the
number of CBO is not possible on Meteor Lake and Panther
Lake. Therefore, we instead compute the effective way size as the
biggest of power of two of the way size which works across all three
platforms.
The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' is introduced to
control this behavior.
The issue addressed by this commit can be observed with the following
experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to
0x400000 (4 MB).
The number of ways that used to be computed is round(0x400000 /
0x180000) = round(2.66) = 3. 3 ways were mapped to cover the 0x400000
NEM+ region. When the bootblock code accesses memory between 3 MB and
4 MB, the core would raise a page fault exception.
The right computation is: 0x400000 / eff_way_size(0x100000) = 4. 4
ways needs to be mapped to cover the entire 0x400000 NEM+ region.
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
2 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83946/13
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Sergii Dmytruk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/67065?usp=email )
Change subject: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
......................................................................
Patch Set 42:
(1 comment)
Patchset:
PS38:
> Unfortunately, this is not enough, booting fails early with very little useful information. […]
The commit message was updated some time ago, but I forgot to mark this as done.
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