coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
by Kevin Yang (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Derek Huang, Eric Lai, Felix Held, Ivan Chen, Paul Menzel. Kevin Yang has posted comments on this change by Kevin Yang. ( https://review.coreboot.org/c/coreboot/+/84232?usp=email ) Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support ...................................................................... Patch Set 5: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84232/comment/328d7bca_edea948a?us… : PS4, Line 9: no port > Thank you. Please amend the message accordingly. Done https://review.coreboot.org/c/coreboot/+/84232/comment/e6b226c8_3a3dfda5?us… : PS4, Line 14: flash and check boot log on DUT. > Thank you. Please amend the message accordingly. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Gerrit-Change-Number: 84232 Gerrit-PatchSet: 5 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 19 Sep 2024 01:21:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/brox/var/lotso: Fix goodix touchscreen power off sequence
by Kun Liu (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Karthik Ramasubramanian, Shelley Chen. Kun Liu has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/84412?usp=email ) Change subject: mb/google/brox/var/lotso: Fix goodix touchscreen power off sequence ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84412/comment/8bb62e29_b02c03bb?us… : PS2, Line 9: Power off does not seem to use the ACPI _OFF function > Did you try to use "has_power_resource" = "1" in the concerned touchscreen device in the override tr […] use "has_power_resource" = "1",add reset delay does not take effect,the result is as follows:https://partnerissuetracker.corp.google.com/issues/364193909#commen…, so use SMI handler to manage the power. -- To view, visit https://review.coreboot.org/c/coreboot/+/84412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0108be4e5e7c0265aae0f16fd4e2b7cbe5936112 Gerrit-Change-Number: 84412 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 01:21:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
by Kevin Yang (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Derek Huang, Eric Lai, Felix Held, Ivan Chen, Kevin Yang. Hello Derek Huang, Eric Lai, Felix Held, Ivan Chen, Karthik Ramasubramanian, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84232?usp=email to look at the new patch set (#5). Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support ...................................................................... mb/google/dedede/var/beadrix: Add LTE only daughterboard support Due to beadrix DB has C1 port before, and add FW_CONFIG with out C1 port for LTE sku. BUG=b:364431483 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Set fw config to DB_PORTS_LTE and check 1.fw_config match found: DB_PORTS=DB_PORTS_LTE <= show LTE present message 2.USB3 port 3: enabled 1 <= LTE port enable Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Signed-off-by: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/beadrix/gpio.c M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84232/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Gerrit-Change-Number: 84232 Gerrit-PatchSet: 5 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
by Knox Chiou (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Xinxiong Xu, Yang Wu, Yu-Ping Wu. Knox Chiou has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84342?usp=email ) Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186 ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/corsola/boardid.c: https://review.coreboot.org/c/coreboot/+/84342/comment/20c7ebc9_f3df2f4b?us… : PS6, Line 131: BOARD_GOOGLE_SQUIRTLE > If we don't want Squirtle to be an exception, can we apply the same modification to Voltorb? We can […] Sounds good from my end, as long as you could ensure the FW match with OS in the future. Then it will be more cleaner from coreboot end. Please make sure there's sufficient comment in boxster and kernel to avoid future maintenance efforts.. -- To view, visit https://review.coreboot.org/c/coreboot/+/84342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91306d3abd508e104851916882fb36a4fd302036 Gerrit-Change-Number: 84342 Gerrit-PatchSet: 6 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 01:12:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Knox Chiou <knoxchiou(a)google.com> Comment-In-Reply-To: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
by Xinxiong Xu (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Hung-Te Lin, Knox Chiou, Paul Menzel, Yang Wu, Yu-Ping Wu. Xinxiong Xu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84342?usp=email ) Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186 ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/corsola/boardid.c: https://review.coreboot.org/c/coreboot/+/84342/comment/a6575902_7a4179d8?us… : PS6, Line 131: BOARD_GOOGLE_SQUIRTLE > Yes if the schedule can be met, otherwise there will be 2 exceptions. […] If we don't want Squirtle to be an exception, can we apply the same modification to Voltorb? We can add 0x7FFFFEFF to the config.star file and support both 0x7FFFFEFF and 0x7FFFFFFF in the same DTS configuration, ensuring consistency. Since we need to add 0x7FFFFEFF to Squirtle's config.star, and also add 0x7FFFFEFF to the DTS that supports 0x7FFFFFFF, this shouldn't cause any confusion. In that case, there will be no need to add exceptions on the coreboot side. What do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/84342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91306d3abd508e104851916882fb36a4fd302036 Gerrit-Change-Number: 84342 Gerrit-PatchSet: 6 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 00:41:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Knox Chiou <knoxchiou(a)google.com> Comment-In-Reply-To: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
by Knox Chiou (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Xinxiong Xu, Yang Wu, Yu-Ping Wu. Knox Chiou has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84342?usp=email ) Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186 ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/corsola/boardid.c: https://review.coreboot.org/c/coreboot/+/84342/comment/44817dd4_ee74778d?us… : PS6, Line 131: BOARD_GOOGLE_SQUIRTLE > Although Squirlte has only one DTS, since 0x7FFFFEFF is not configured in config. […] Yes if the schedule can be met, otherwise there will be 2 exceptions. As bug mentioned, 0x7FFFFEFF needs to be defined at the program level within boxster and exposed externally. This will ensure Corsola and Staryu utilize the same configuration going forward. -- To view, visit https://review.coreboot.org/c/coreboot/+/84342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91306d3abd508e104851916882fb36a4fd302036 Gerrit-Change-Number: 84342 Gerrit-PatchSet: 6 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 00:06:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Jérémy Compostella (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Cliff Huang, Felix Held, Paul Menzel, Pranava Y N, Saurabh Mishra, Subrata Banik. Jérémy Compostella has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... Patch Set 183: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/gpio.c: https://review.coreboot.org/c/coreboot/+/83419/comment/a65ddb71_9f7639ad?us… : PS180, Line 49: CROS_GPIO_DEVICE0_NAME > > why `DEVICE0` ? […] Sure but then this CL will not compile anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 183 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 19 Sep 2024 00:04:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/google/fatcat: Add override tree
by Jérémy Compostella (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Pranava Y N, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84407?usp=email ) Change subject: mb/google/fatcat: Add override tree ...................................................................... Patch Set 4: (12 comments) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84407/comment/7bd373ac_dbbfe9ec?us… : PS1, Line 3: # GPE configuration : # Note that GPE events called out in ASL code rely on this : # route. i.e. If this route changes then the affected GPE : # offset bits also need to be changed. : register "pmc_gpe0_dw0" = "GPP_B" : register "pmc_gpe0_dw1" = "GPP_D" : register "pmc_gpe0_dw2" = "GPP_E" > this should do to baseboard devicetree Done https://review.coreboot.org/c/coreboot/+/84407/comment/3cf95aa1_4eb4267b?us… : PS1, Line 40: : register "tcss_cap_policy[0]" = "7" : register "tcss_cap_policy[1]" = "7" : register "tcss_cap_policy[2]" = "7" : register "tcss_cap_policy[3]" = "7" > Please let me know what this is. cf. https://review.coreboot.org/c/coreboot/+/84419 https://review.coreboot.org/c/coreboot/+/84407/comment/70eacce4_e804c88b?us… : PS1, Line 45: : # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f : register "gen1_dec" = "0x00fc0801" : register "gen2_dec" = "0x000c0201" : # EC memory map range is 0x900-0x9ff : register "gen3_dec" = "0x00fc0901" > same as previous comment Done https://review.coreboot.org/c/coreboot/+/84407/comment/229f1a07_5dae4ab2?us… : PS1, Line 52: # This disabled autonomous GPIO power management for early PO : register "gpio_override_pm" = "1" : register "gpio_pm[COMM_0]" = "0" : register "gpio_pm[COMM_1]" = "0" : register "gpio_pm[COMM_3]" = "0" : register "gpio_pm[COMM_4]" = "0" : register "gpio_pm[COMM_5]" = "0" > we don't need to override to zero value, unless defined the value should be zero Done https://review.coreboot.org/c/coreboot/+/84407/comment/c2e5c3e7_a913e179?us… : PS1, Line 69: # Enable s0ix : register "s0ix_enable" = "1" > this should do to baseboard devicetree Done https://review.coreboot.org/c/coreboot/+/84407/comment/158050e6_cd37c8f5?us… : PS1, Line 114: # Intel Common SoC Config > we generally maintain a table to understand the I2Cx mapping, can you please apply that here as well […] Done https://review.coreboot.org/c/coreboot/+/84407/comment/cf8bfdf4_bb62c485?us… : PS1, Line 151: device ref dtt off end : device ref npu on end : device ref iaa off end : : device ref heci1 on end : > you can move these to baseboard Done https://review.coreboot.org/c/coreboot/+/84407/comment/bac5177d_7b78f6db?us… : PS1, Line 223: > please use consistent tab Done https://review.coreboot.org/c/coreboot/+/84407/comment/c036bbb5_6098eb79?us… : PS1, Line 246: device ref pcie_rp1 off : # register "pcie_rp[PCIE_RP(1)]" = "{ : # .clk_src = 3, : # .clk_req = 3, : # .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, : # }" : end # Gbe > please don't add GBE support which is non-POR for Chrome, if you wish to keep RP0 enabled then keep […] Done https://review.coreboot.org/c/coreboot/+/84407/comment/a565a17c_80f8ed84?us… : PS1, Line 305: device ref pcie_rp9 on : register "pcie_rp[PCIE_RP(9)]" = "{ : .clk_src = 1, : .clk_req = 1, : .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, : }" : chip soc/intel/common/block/pcie/rtd3 : register "is_storage" = "true" : register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" : register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" : register "srcclk_pin" = "1" : device generic 0 on end : end : end # Gen5 M.2 SSD / x4 PCIe slot > please don't need Gen5 support. […] Done https://review.coreboot.org/c/coreboot/+/84407/comment/873e3e0f_030b6714?us… : PS1, Line 330: lnlrvp_ish > please don't enable everything as part of base CL. […] Done https://review.coreboot.org/c/coreboot/+/84407/comment/ef676e24_760a5b8b?us… : PS1, Line 654: device ref hda on : chip drivers/intel/soundwire : device generic 0 on : chip drivers/soundwire/alc711 : # SoundWire Link 1 ID 1 : register "desc" = ""Headset Codec"" : device generic 1.1 on end : end : end : end : chip drivers/generic/max98357a : register "hid" = ""MX98357A"" : register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" : register "sdmode_delay" = "5" : device generic 0 on end : end : chip drivers/generic/max98357a : register "hid" = ""MX98360A"" : register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" : register "sdmode_delay" = "5" : device generic 0 on end : end : end : : end > please use consistent spacing Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84407?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d53 Gerrit-Change-Number: 84407 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 00:02:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/ptl: Provide the TCSS port policy setting options
by Jérémy Compostella (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84419?usp=email ) Change subject: soc/intel/ptl: Provide the TCSS port policy setting options ...................................................................... soc/intel/ptl: Provide the TCSS port policy setting options Each TCSS port can be associated a setting via the tcss_cap_policy device tree field. The setting can be picked within five values listed by this commit. BUG=b/348678529 TEST=fatcat board build tcss_cap_policy[0]=TCSS_TYPE_C_PORT_FULL_FUN Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d56 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/include/soc/tcss.h 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/84419/1 diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 27d766f..85dcccd 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -16,6 +16,7 @@ #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/serialio.h> +#include <soc/tcss.h> #include <soc/usb.h> #include <stdint.h> diff --git a/src/soc/intel/pantherlake/include/soc/tcss.h b/src/soc/intel/pantherlake/include/soc/tcss.h index 79604bc..a1d72b8 100644 --- a/src/soc/intel/pantherlake/include/soc/tcss.h +++ b/src/soc/intel/pantherlake/include/soc/tcss.h @@ -16,4 +16,12 @@ #define BIAS_CTRL_VW_INDEX_SHIFT 24 #define BIAS_CTRL_BIT_POS_SHIFT 16 +enum { + TCSS_TYPE_C_PORT_DISABLE, + TCSS_TYPE_C_PORT_DP_ONLY, + TCSS_TYPE_C_PORT_NO_TBT, + TCSS_TYPE_C_PORT_NO_PCIE, + TCSS_TYPE_C_PORT_FULL_FUN = 7 +}; + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/84419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d56 Gerrit-Change-Number: 84419 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: mb/google/fatcat: Add override tree
by Jérémy Compostella (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Jérémy Compostella, Pranava Y N. Hello Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84407?usp=email to look at the new patch set (#4). Change subject: mb/google/fatcat: Add override tree ...................................................................... mb/google/fatcat: Add override tree BUG=b:348678529 TEST=Boot on google fatcat board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d53 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb A src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 3 files changed, 670 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/84407/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84407?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d53 Gerrit-Change-Number: 84407 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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