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[S] Change in coreboot[main]: soc/amd/*: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84587?usp=email ) Change subject: soc/amd/*: Explicitly include static.h for config_of_soc ...................................................................... soc/amd/*: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I9db5d80ca0a75ccff3b8e24db0ccbd6b36c84dcb Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/acpi.c M src/soc/amd/glinda/fsp_m_params.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/mendocino/fsp_m_params.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/phoenix/fsp_m_params.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/fch.c M src/soc/amd/picasso/fsp_m_params.c M src/soc/amd/picasso/root_complex.c 15 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/84587/1 diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index f60512d..4481c46 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -15,6 +15,7 @@ #include <cpu/amd/cpuid.h> #include <device/device.h> #include <soc/iomap.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index f86be94..5349a16 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -10,6 +10,7 @@ #include <fsp/api.h> #include <soc/platform_descriptors.h> #include <soc/pci_devs.h> +#include <static.h> #include <string.h> #include <types.h> #include <vendorcode/amd/fsp/cezanne/FspUsb.h> diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 04fb90c..d9999b9 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -9,6 +9,7 @@ #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> +#include <static.h> #include <stdint.h> #include "chip.h" diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index eb1d478..dbe610c 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -18,6 +18,7 @@ #include <cpu/amd/cpuid.h> #include <device/device.h> #include <soc/iomap.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c index 843a2d9..1d297d4 100644 --- a/src/soc/amd/glinda/fsp_m_params.c +++ b/src/soc/amd/glinda/fsp_m_params.c @@ -13,6 +13,7 @@ #include <fsp/api.h> #include <soc/platform_descriptors.h> #include <soc/pci_devs.h> +#include <static.h> #include <string.h> #include <types.h> #include <vendorcode/amd/fsp/glinda/FspUsb.h> diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 776fc32..953e089 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -11,6 +11,7 @@ #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> +#include <static.h> #include <stdint.h> #include "chip.h" diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index e7f0d96..9982d84 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -17,6 +17,7 @@ #include <cpu/amd/cpuid.h> #include <device/device.h> #include <soc/iomap.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index 6582a7c..8a76669 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -12,6 +12,7 @@ #include <fsp/api.h> #include <soc/platform_descriptors.h> #include <soc/pci_devs.h> +#include <static.h> #include <string.h> #include <types.h> #include <vendorcode/amd/fsp/mendocino/FspUsb.h> diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index a7cbe51..65ae507 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -12,6 +12,7 @@ #include <device/pci.h> #include <fsp/amd_misc_data.h> #include <soc/iomap.h> +#include <static.h> #include <stdint.h> #include "chip.h" diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index c6e06be..a182dfbb 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -18,6 +18,7 @@ #include <cpu/amd/cpuid.h> #include <device/device.h> #include <soc/iomap.h> +#include <static.h> #include <types.h> #include <vendorcode/amd/opensil/opensil.h> #include "chip.h" diff --git a/src/soc/amd/phoenix/fsp_m_params.c b/src/soc/amd/phoenix/fsp_m_params.c index 06c7127..45a038e 100644 --- a/src/soc/amd/phoenix/fsp_m_params.c +++ b/src/soc/amd/phoenix/fsp_m_params.c @@ -13,6 +13,7 @@ #include <fsp/api.h> #include <soc/platform_descriptors.h> #include <soc/pci_devs.h> +#include <static.h> #include <string.h> #include <types.h> #include <vendorcode/amd/fsp/phoenix/FspUsb.h> diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 7fed3bd..724121c 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -11,6 +11,7 @@ #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> +#include <static.h> #include <stdint.h> #include "chip.h" diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 8952c16..3550349 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -21,6 +21,7 @@ #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> #include <soc/pci_devs.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/amd/picasso/fsp_m_params.c b/src/soc/amd/picasso/fsp_m_params.c index 0be815e..d1280fd 100644 --- a/src/soc/amd/picasso/fsp_m_params.c +++ b/src/soc/amd/picasso/fsp_m_params.c @@ -8,6 +8,7 @@ #include <soc/platform_descriptors.h> #include <soc/pci_devs.h> #include <soc/fsp.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index a3bd729..aa75f0b 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -8,6 +8,7 @@ #include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> +#include <static.h> #include <stdint.h> #include <soc/iomap.h> #include "chip.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/84587?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9db5d80ca0a75ccff3b8e24db0ccbd6b36c84dcb Gerrit-Change-Number: 84587 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/intel/*: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Patrick Rudolph, Pranava Y N, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Werner Zeh. Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84586?usp=email ) Change subject: soc/intel/*: Explicitly include static.h for config_of_soc ...................................................................... soc/intel/*: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I03e42689487c6d63436d9c2945558073aae87cd1 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/pmc.c M src/soc/intel/alderlake/pmutil.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/systemagent.c M src/soc/intel/apollolake/chip.c M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/pmc.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/pantherlake/acpi.c M src/soc/intel/pantherlake/pmc.c M src/soc/intel/pantherlake/pmutil.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 34 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/84586/1 diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index dcf8a7c..ba3a5bc 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -19,6 +19,7 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> #include <cpu/cpu.h> #include <types.h> diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 255082f..00c683c 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -24,6 +24,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> enum alderlake_model { diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8c4c291..8db0a92 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -32,6 +32,7 @@ #include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <static.h> #include <stdlib.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index f0b35db..8930a06 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -20,6 +20,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <static.h> #include <stdint.h> #include <bootstate.h> diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 54e9107..050fd5b 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -30,6 +30,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 969e15f..fc9721c 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -22,6 +22,7 @@ #include <soc/pcie.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <static.h> #include <string.h> #include "ux.h" diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index b08e3a3..be0c699 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -19,6 +19,7 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <spi_flash.h> +#include <static.h> #include <stddef.h> /* diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1d15eec..ab5b5d8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -35,6 +35,7 @@ #include <soc/pm.h> #include <soc/systemagent.h> #include <spi-generic.h> +#include <static.h> #include <timer.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index be058d0..46e36c7 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -11,6 +11,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <static.h> #include "../chip.h" /* This sequence signals the PUNIT to start running. */ diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index b8a2c8c..f932959 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -15,6 +15,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/microcode.h> #include <cpu/intel/common/common.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index e1eede2..a6c1390 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -16,6 +16,7 @@ #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 0a9de86..1770167 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -13,6 +13,7 @@ #include <intelblocks/msr.h> #include <smp/node.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> #define CPUID_PROCESSOR_FREQUENCY 0X16 diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 49e418a..4e85d01 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -14,6 +14,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> bool cpu_soc_is_in_untrusted_mode(void) diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 90d1823..7b715f8 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -15,6 +15,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> /* SATA DEVSLP idle timeout default values */ diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 8dd2682..d01f1d7 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -14,6 +14,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> bool cpu_soc_is_in_untrusted_mode(void) diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 50fc136..85664ce 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -14,6 +14,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index a3ee198..e3aa44e 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -20,6 +20,7 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index bf1d9d5..7d4d504 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -31,6 +31,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <static.h> #include <stdlib.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/meteorlake/pmc.c b/src/soc/intel/meteorlake/pmc.c index 5c4fa2c..837a8f3 100644 --- a/src/soc/intel/meteorlake/pmc.c +++ b/src/soc/intel/meteorlake/pmc.c @@ -15,6 +15,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <static.h> #include <stdint.h> #include <bootstate.h> diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 09fb46b..8e91b27 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -24,6 +24,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 917503e..bc7c20b 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -26,6 +26,7 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <static.h> #include <string.h> #include <ux_locales.h> diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c index fd17ef5..05479ef 100644 --- a/src/soc/intel/pantherlake/acpi.c +++ b/src/soc/intel/pantherlake/acpi.c @@ -20,6 +20,7 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/pantherlake/pmc.c b/src/soc/intel/pantherlake/pmc.c index 1c1ca5d..de6bf0c 100644 --- a/src/soc/intel/pantherlake/pmc.c +++ b/src/soc/intel/pantherlake/pmc.c @@ -15,6 +15,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <static.h> #include <stdint.h> #define PMC_HID "INTC1026" diff --git a/src/soc/intel/pantherlake/pmutil.c b/src/soc/intel/pantherlake/pmutil.c index 892972c..888bb56 100644 --- a/src/soc/intel/pantherlake/pmutil.c +++ b/src/soc/intel/pantherlake/pmutil.c @@ -24,6 +24,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index e0381e8..3a60ada 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -17,6 +17,7 @@ #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d1cc6f9..a6844e0 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -28,6 +28,7 @@ #include <soc/ramstage.h> #include <soc/systemagent.h> #include <soc/usb.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5cf48ea..afe1c24 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -21,6 +21,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index d203bda..3708f05 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -12,6 +12,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 3d0f0e9..0c6f36e 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -20,6 +20,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> bool cpu_soc_is_in_untrusted_mode(void) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index d5472dd..7c35b7a 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -26,6 +26,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/tcss.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 00b5315..5ebd46d 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -16,6 +16,7 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <static.h> #include <string.h> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index e0c2f3b..b6b8e00 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -8,6 +8,7 @@ #include <soc/chip_common.h> #include <soc/pci_devs.h> #include <soc/util.h> +#include <static.h> #include <stdint.h> #include <stdio.h> #include <stdlib.h> diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 2a85032..ffcb052 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -13,6 +13,7 @@ #include <soc/pci_devs.h> #include <soc/intel/common/smbios.h> #include <soc/soc_util.h> +#include <static.h> #include <string.h> #include "chip.h" diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index b05c7e7..4762231 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -18,6 +18,7 @@ #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/soc_pch.h> +#include <static.h> #include <string.h> #include <soc/config.h> #include <soc/soc_util.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/84586?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03e42689487c6d63436d9c2945558073aae87cd1 Gerrit-Change-Number: 84586 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Shuo Liu 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1 0

[M] Change in coreboot[main]: nb/intel/*: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 30 Sep '24

30 Sep '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84585?usp=email ) Change subject: nb/intel/*: Explicitly include static.h for config_of_soc ...................................................................... nb/intel/*: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: Iac8063d2021af83203be8a10b2962c9fb3dd106a Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/northbridge/intel/haswell/broadwell_mrc/raminit.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c A src/northbridge/intel/sandybridge/early_gma.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/raminit_native.c 8 files changed, 101 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/84585/1 diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c index 1ed42485..beae496 100644 --- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c @@ -20,6 +20,7 @@ #include <northbridge/intel/haswell/raminit.h> #include <smbios.h> #include <spd.h> +#include <static.h> #include <security/vboot/vboot_common.h> #include <commonlib/region.h> #include <southbridge/intel/lynxpoint/me.h> diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 9a7b7fe..3d5e46c 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -18,6 +18,7 @@ #include <northbridge/intel/haswell/raminit.h> #include <smbios.h> #include <spd.h> +#include <static.h> #include <security/vboot/vboot_common.h> #include <commonlib/region.h> #include <southbridge/intel/lynxpoint/me.h> diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c index 19ec585..2271705 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c @@ -7,6 +7,7 @@ #include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c index c53ea12..a422591 100644 --- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c +++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c @@ -8,6 +8,7 @@ #include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/northbridge/intel/sandybridge/early_gma.c b/src/northbridge/intel/sandybridge/early_gma.c new file mode 100644 index 0000000..30da5ed --- /dev/null +++ b/src/northbridge/intel/sandybridge/early_gma.c @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <device/mmio.h> +#include <console/console.h> +#include <bootmode.h> +#include <cpu/intel/model_206ax/model_206ax.h> +#include <delay.h> +#include <device/device.h> +#include <static.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <drivers/intel/gma/libgfxinit.h> +#include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <static.h> +#include <types.h> +#include <cpu/x86/mtrr.h> + +#include "chip.h" +#include "sandybridge.h" +#include "early_graphics.h" + +static struct resource *gtt_res = NULL; + +static struct resource early_gtt_res = { + .base = CONFIG_GFX_GMA_DEFAULT_MMIO +}; + +static u32 early_gtt_read(u32 reg) +{ + void *p = res2mmio(gtt_res, reg, 0); + printk(BIOS_DEBUG, "gtt_read(%p)\n", p); + return read32(p); +} + +static void early_gtt_write(u32 reg, u32 data) +{ + void *p = res2mmio(gtt_res, reg, 0); + printk(BIOS_DEBUG, "gtt_write(%p, 0x%08x)\n", p, data); + write32(p, data); +} + +void early_graphics_panel_init(void) +{ + pci_devfn_t host_bridge = PCI_DEV(0, 0, 0); + printk(BIOS_DEBUG, "Host Bridge DEVEN: 0x%04x\n", pci_read_config32(host_bridge, 0x54)); + display_mtrrs(); + gtt_res = &early_gtt_res; + const struct northbridge_intel_sandybridge_config *conf = config_of_soc(); + u32 reg32; + + /* Setup Panel Power On Delays */ + printk(BIOS_DEBUG, "Setup Panel Power On Delays\n"); + reg32 = early_gtt_read(0xc7208); + if (!reg32) { + reg32 = (conf->gpu_panel_port_select & 0x3) << 30; + reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + early_gtt_write(0xc7208, reg32); + } + + /* Setup Panel Power Off Delays */ + printk(BIOS_DEBUG, "Setup Panel Power Off Delays\n"); + reg32 = early_gtt_read(0xc720c); + if (!reg32) { + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + early_gtt_write(0xc720c, reg32); + } + + /* Setup Panel Power Cycle Delay */ + printk(BIOS_DEBUG, "Setup Panel Power Cycle Delay\n"); + if (conf->gpu_panel_power_cycle_delay) { + reg32 = early_gtt_read(0xc7210); + reg32 &= ~0xff; + reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; + early_gtt_write(0xc7210, reg32); + } + + /* Enable Backlight if needed */ + printk(BIOS_DEBUG, "Enable Backlight\n"); + if (conf->gpu_cpu_backlight) { + early_gtt_write(0x48250, (1 << 31)); + early_gtt_write(0x48254, conf->gpu_cpu_backlight); + } + if (conf->gpu_pch_backlight) { + early_gtt_write(0xc8250, (1 << 31)); + early_gtt_write(0xc8254, conf->gpu_pch_backlight); + } +} diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index d5e1a7c..9ec8fb6f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -15,6 +15,7 @@ #include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <static.h> #include <cpu/x86/msr.h> #include <types.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 98b3028..b81716a 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -19,6 +19,7 @@ #include <mrc_cache.h> #include <spd.h> #include <smbios.h> +#include <static.h> #include <stddef.h> #include <stdint.h> #include <timestamp.h> diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index ecae91b..ed11945 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -9,6 +9,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <northbridge/intel/sandybridge/chip.h> +#include <static.h> #include <stdbool.h> #include <stdint.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/84585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac8063d2021af83203be8a10b2962c9fb3dd106a Gerrit-Change-Number: 84585 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[XS] Change in coreboot[main]: tree: Use boolean for dptf_enable
by Nico Huber (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Eric Lai, Erik van den Bogaert, Frans Hendriks, Jakub Czapiga, Jayvik Desai, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Maxim, Michał Żygowski, Nick Vaccaro, Piotr Król, Pranava Y N, Rishika Raj, Subrata Banik, Tarun, Werner Zeh. Nico Huber has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84161?usp=email ) Change subject: tree: Use boolean for dptf_enable ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Ok, now I've just changed `int dptf_enable;` with `bool dptf_enable;` […] Well, technically there's nothing wrong with that. I assume it would leave some devicetrees look inconsistent now that other patches already landed. Ok for me would be if we find consensus *before* doing bulk changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/84161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Gerrit-Change-Number: 84161 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 29 Sep 2024 23:45:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[M] Change in coreboot[main]: [RFC] soc/intel/fsp_reset: Drop global-reset sanity check
by Nico Huber (Code Review) 30 Sep '24

30 Sep '24

Nico Huber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84558?usp=email ) Change subject: [RFC] soc/intel/fsp_reset: Drop global-reset sanity check ...................................................................... Abandoned was for discussion only which seems to have settled -- To view, visit https://review.coreboot.org/c/coreboot/+/84558?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cc5a70f1a673c58dc6ffa65e707b080f81fce79 Gerrit-Change-Number: 84558 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: [RFC] soc/intel/fsp_reset: Drop global-reset sanity check
by Nico Huber (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Pranava Y N, Ronak Kanabar, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh. Nico Huber has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/84558?usp=email ) Change subject: [RFC] soc/intel/fsp_reset: Drop global-reset sanity check ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/fsp_reset.c: https://review.coreboot.org/c/coreboot/+/84558/comment/edcee8fa_8bd7abdc?us… : PS1, Line 78: /* Use RESET_REQUIRED_3 status for global resets. Needs : to be kept in sync with chipset_handle_reset() above. */ : return FSP_STATUS_RESET_REQUIRED_3; > So to get rid of the check, I would suggest to re-architecture a bit further: > > 1. Have our own reset type enum reset_type { warm, cold, global, none } or enum soc_reset_type ? > 2. Return this type in fsp_get_pch_reset_status(). > 3. Have a fsp_status_to_reset_type() function converting a reset status to a enum reset_type > 4. Simplify fsp_handle_reset(): > 1. Use fsp_status_to_reset_type() > 2. print the actual type of reset (warm, cold or global) instead of the status (which is my opinion is an improvement) I had something similar in mind when I wrote about encapsulation on your patch. If somebody wants to look into that, I suggest we first discuss where to draw which line. > 3. Call global_reset() directly ? Why do we call chipset_handle_reset() in the first place ? I think it was implemented like this to separate things like they are in the FSP EAS and the integration guides. fsp_handle_reset() implements the EAS, while chipset_handle_reset() implements the integration guide. -- To view, visit https://review.coreboot.org/c/coreboot/+/84558?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cc5a70f1a673c58dc6ffa65e707b080f81fce79 Gerrit-Change-Number: 84558 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 29 Sep 2024 22:54:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: stddef.h: Introduce nullptr constant
by Felix Singer (Code Review) 29 Sep '24

29 Sep '24

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[XS] Change in coreboot[main]: stddef.h: Introduce nullptr constant
by Felix Singer (Code Review) 29 Sep '24

29 Sep '24

Attention is currently required from: Elyes Haouas, Jakub Czapiga, Julius Werner, Martin L Roth, Maximilian Brune, Nico Huber. Felix Singer has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/83459?usp=email ) Change subject: stddef.h: Introduce nullptr constant ...................................................................... Patch Set 26: (1 comment) File src/include/stddef.h: https://review.coreboot.org/c/coreboot/+/83459/comment/36d09bed_dbfbcf51?us… : PS26, Line 25: #define nullptr ((void *)0) > By my understanding, leadership is against changing `NULL` by `nullptr` and not using new constants […] I also don't think people are against using it. It's just that there is no real advantage of doing this major move at the moment, but I think there is no problem with this conditional macro. Also, it doesn't give us new functionality, but it rather makes us more complaint to the C23 standard. That's a difference. @jwerner@chromium.org @maximilian.brune@9elements.com Do you remember the outcome of that discussion? -- To view, visit https://review.coreboot.org/c/coreboot/+/83459?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07db866bebfd25f1a60d18a3228ada2957500234 Gerrit-Change-Number: 83459 Gerrit-PatchSet: 26 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 29 Sep 2024 15:36:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: tree: Use boolean for dptf_enable
by Elyes Haouas (Code Review) 29 Sep '24

29 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Erik van den Bogaert, Frans Hendriks, Jakub Czapiga, Jayvik Desai, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Maxim, Michał Żygowski, Nick Vaccaro, Nico Huber, Piotr Król, Pranava Y N, Rishika Raj, Subrata Banik, Tarun, Werner Zeh. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84161?usp=email ) Change subject: tree: Use boolean for dptf_enable ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > > For my understanding, the natural language for "dptf_enable" would be "yes/no". […] Ok, now I've just changed `int dptf_enable;` with `bool dptf_enable;` Is it ok for you? -- To view, visit https://review.coreboot.org/c/coreboot/+/84161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Gerrit-Change-Number: 84161 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 29 Sep 2024 14:34:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: stddef.h: Introduce nullptr constant
by Elyes Haouas (Code Review) 29 Sep '24

29 Sep '24

Attention is currently required from: Felix Singer, Jakub Czapiga, Martin L Roth, Nico Huber. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/83459?usp=email ) Change subject: stddef.h: Introduce nullptr constant ...................................................................... Patch Set 26: (1 comment) File src/include/stddef.h: https://review.coreboot.org/c/coreboot/+/83459/comment/dfc1a64b_9dbb1550?us… : PS26, Line 25: #define nullptr ((void *)0) > Just checking, I thought we decided against using `nullptr`/`nullptr_t` in […] By my understanding, leadership is against changing `NULL` by `nullptr` and not using new constants that modern C provides. This allow using new "functionality" without changing old coding style for null pointer. -- To view, visit https://review.coreboot.org/c/coreboot/+/83459?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07db866bebfd25f1a60d18a3228ada2957500234 Gerrit-Change-Number: 83459 Gerrit-PatchSet: 26 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Comment-Date: Sun, 29 Sep 2024 14:26:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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