coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/amd/*: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84587?usp=email ) Change subject: soc/amd/*: Explicitly include static.h for config_of_soc ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Seems to be missing some files that use `config_of_soc` -- To view, visit https://review.coreboot.org/c/coreboot/+/84587?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9db5d80ca0a75ccff3b8e24db0ccbd6b36c84dcb Gerrit-Change-Number: 84587 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 30 Sep 2024 06:29:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-S programming
by Subrata Banik (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84552?usp=email ) Change subject: soc/intel/pantherlake: Add FSP-S programming ...................................................................... Patch Set 11: (19 comments) File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84552/comment/d533ee4b_6b7f144a?us… : PS11, Line 102: ANY_PIRQ any reason for not using fixed IRQ for DPTF ? https://review.coreboot.org/c/coreboot/+/84552/comment/47252a31_31987f82?us… : PS11, Line 118: }, Why did we skipped IRQ assignment for PCIE RP 11 and 12 ? Ideally you can use PTL-UH config to implement PCIE RP > 10 as well https://review.coreboot.org/c/coreboot/+/84552/comment/0326f9a0_c76a7702?us… : PS11, Line 136: { did we remove ISH intentionally ? https://review.coreboot.org/c/coreboot/+/84552/comment/f4cf2e5f_682041bf?us… : PS11, Line 250: static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, : const struct soc_intel_pantherlake_config *config) : { : const struct microcode *microcode; : size_t length; : : if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) : s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); : : if (CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS)) { : /* Locate microcode and pass to FSP-S for 2nd microcode loading */ : microcode = intel_microcode_find(); : if (!microcode) : return; : : length = get_microcode_size(microcode); : if (!length) : return; : : /* Update CPU Microcode patch base address/size */ : s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode; : s_cfg->MicrocodeRegionSize = (uint32_t)length; : } : } ``` static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_meteorlake_config *config) { const struct microcode *microcode_file; size_t microcode_len; /* Locate microcode and pass to FSP-S for 2nd microcode loading */ microcode_file = intel_microcode_find(); if (microcode_file != NULL) { microcode_len = get_microcode_size(microcode_file); if (microcode_len != 0) { /* Update CPU Microcode patch base address/size */ s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; } } } static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_meteorlake_config *config) { /* * FIXME: FSP assumes ownership of the APs (Application Processors) * upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. * Hence, pass a valid pointer to the CpuMpPpi UPD unconditionally. * This would avoid APs from getting hijacked by FSP while coreboot * decides to set SkipMpInit UPD. */ s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); /* * Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature * programming. */ if (CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS)) fill_fsps_microcode_params(s_cfg, config); } ``` https://review.coreboot.org/c/coreboot/+/84552/comment/ff29395a_310bb97c?us… : PS11, Line 301: max_port = get_max_tcss_port(); : for (i = 0; i < max_port; i++) ``` for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { ``` https://review.coreboot.org/c/coreboot/+/84552/comment/ee55e2ae_169eefe7?us… : PS11, Line 323: 0 `CONFIG_SOC_INTEL_CRASHLOG` ??? https://review.coreboot.org/c/coreboot/+/84552/comment/a061008a_e45eb561?us… : PS11, Line 381: s_cfg->Device4Enable = is_devfn_enabled(PCI_DEVFN_DPTF); ``` /* Set TccActivationOffset */ s_cfg->TccActivationOffset = config->tcc_offset; ``` https://review.coreboot.org/c/coreboot/+/84552/comment/2fdbc9b4_b8b0972c?us… : PS11, Line 383: don't we need the API below? ``` static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_meteorlake_config *config) { ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; } ``` https://review.coreboot.org/c/coreboot/+/84552/comment/3226c1f1_6a9995e0?us… : PS11, Line 444: : /* Settings per board. */ https://review.coreboot.org/c/coreboot/+/71643 https://review.coreboot.org/c/coreboot/+/84552/comment/72f6ad0b_1a709db0?us… : PS11, Line 495: s_cfg->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); : s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); https://review.coreboot.org/c/coreboot/+/70423 https://review.coreboot.org/c/coreboot/+/84552/comment/2e23e90a_af33acc3?us… : PS11, Line 511: can you please add `fill_fsps_ufs_params` https://review.coreboot.org/c/coreboot/+/84552/comment/2bbbbe77_a84efb97?us… : PS11, Line 536: fill_fsps_misc_power_params need to port Cls if not, please justify 1. https://review.coreboot.org/c/coreboot/+/69680 2. https://review.coreboot.org/c/coreboot/+/71653 3. https://review.coreboot.org/c/coreboot/+/76826 4. https://review.coreboot.org/c/coreboot/+/78250 5. https://review.coreboot.org/c/coreboot/+/72709 6. https://review.coreboot.org/c/coreboot/+/73061 https://review.coreboot.org/c/coreboot/+/84552/comment/cab3e07d_5510ac97?us… : PS11, Line 555: /* Fill MIC privacy settings */ does this also applicable when someone choose not to use soundwire interface ? https://review.coreboot.org/c/coreboot/+/84552/comment/90e6b089_88dcc2c4?us… : PS11, Line 564: aix should be either `iaa` or `iax` https://review.coreboot.org/c/coreboot/+/84552/comment/7c2adf75_448b2e65?us… : PS11, Line 567: Iax shouldn't this UPD named as `IaaEnable`? https://review.coreboot.org/c/coreboot/+/84552/comment/e75dca9b_1d1d3033?us… : PS11, Line 570: fill_fsps_pch_pm_params It looks like we didn't have this code in MTL, which makes me think the default update policy was enough to set the correct value? If we do need to override these values, could you add support for chip config instead of hardcoding it? https://review.coreboot.org/c/coreboot/+/84552/comment/94eaadeb_4093b37a?us… : PS11, Line 602: { earlier we were allowing mainboard to override ? it's always like this caller ---> SOC override ---> mainboard override ``` mainboard_update_soc_chip_config ``` https://review.coreboot.org/c/coreboot/+/84552/comment/c712560c_c3eb6654?us… : PS11, Line 642: /* Override settings per board if required. */ : mainboard_update_soc_chip_config(config); follow the previous comment. https://review.coreboot.org/c/coreboot/+/84552/comment/bf55ea5b_58e3f332?us… : PS11, Line 683: efi_uintn_t logo, blt_size; : uint32_t logo_size; : : fsp_convert_bmp_to_gop_blt(&logo, &logo_size, : &supd->FspsConfig.BltBufferAddress, : &blt_size, : &supd->FspsConfig.LogoPixelHeight, : &supd->FspsConfig.LogoPixelWidth); can you please follow to ensure FSP logo ptr and required UPDs are getting filled otherwise FSP won't be able to render the splash screen ``` fsp_convert_bmp_to_gop_blt(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize, &supd->FspsConfig.BltBufferAddress, &supd->FspsConfig.BltBufferSize, &supd->FspsConfig.LogoPixelHeight, &supd->FspsConfig.LogoPixelWidth); ``` if those UPDs are not exposed into the FSP header, please ensure to publish it beforehand, this is hack imo. -- To view, visit https://review.coreboot.org/c/coreboot/+/84552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Gerrit-Change-Number: 84552 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 06:19:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: tree: Use boolean for dptf_enable
by Eric Lai (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Erik van den Bogaert, Jakub Czapiga, Jayvik Desai, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Maxim, Michał Żygowski, Nick Vaccaro, Piotr Król, Pranava Y N, Rishika Raj, Subrata Banik, Tarun, Werner Zeh. Eric Lai has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84161?usp=email ) Change subject: tree: Use boolean for dptf_enable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Gerrit-Change-Number: 84161 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 30 Sep 2024 05:56:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: tree: Use boolean for dptf_enable
by Frans Hendriks (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Eric Lai, Erik van den Bogaert, Jakub Czapiga, Jayvik Desai, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Maxim, Michał Żygowski, Nick Vaccaro, Piotr Król, Pranava Y N, Rishika Raj, Subrata Banik, Tarun, Werner Zeh. Frans Hendriks has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84161?usp=email ) Change subject: tree: Use boolean for dptf_enable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Gerrit-Change-Number: 84161 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 30 Sep 2024 05:48:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brox/jubilant: Modify start-up timing for WWAN RW101R-GL
by Subrata Banik (Code Review) 30 Sep '24

30 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84413?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brox/jubilant: Modify start-up timing for WWAN RW101R-GL ...................................................................... mb/google/brox/jubilant: Modify start-up timing for WWAN RW101R-GL Modify start-up timing for WWAN RW101R-GL to follow spec: PWR_EN H H H FCPO# Tpr H H RESET# L Ton H Tpr: delay for Power stable (>0ms) Ton: delay for reset time (>20ms) BUG=b:349698817 BRANCH=None TEST= Build firmware and verify on jubilant with RW101R-GL Measure the start-up timing sequence to meet spec Boot up in OS, and confirm WWAN can connect to cell site Change-Id: I7aa3e7a172143ff1cebea7f48bda45d4fb2c77f7 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84413 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/variants/jubilant/gpio.c 1 file changed, 19 insertions(+), 7 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/variants/jubilant/gpio.c b/src/mainboard/google/brox/variants/jubilant/gpio.c index 7562b65..aad759d 100644 --- a/src/mainboard/google/brox/variants/jubilant/gpio.c +++ b/src/mainboard/google/brox/variants/jubilant/gpio.c @@ -13,11 +13,9 @@ /* GPP_E17 : [NF2: THC0_SPI1_INT# NF6: USB_C_GPP_E17] ==> WWAN_CFG02 */ PAD_CFG_GPI(GPP_E17, NONE, PLTRST), /* GPP_D7 : SRCCLKREQ2_L ==> WWAN_RF_DISABLE_ODL */ - PAD_CFG_GPO(GPP_D7, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D7, 1, LOCK_CONFIG), /* GPP_D5 : SRCCLKREQ0_L ==> WWAN_SAR_ODL */ PAD_CFG_GPO(GPP_D5, 1, DEEP), - /* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_FCPO_L */ - PAD_CFG_GPO(GPP_F21, 0, DEEP), /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> WWAN_WLAN_COEX1 */ PAD_CFG_GPI(GPP_S4, NONE, DEEP), /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> WWAN_WLAN_COEX2 */ @@ -28,9 +26,11 @@ * GPP_A12 : [NF1: SATAXPCIE1 NF2: SATAGP1 NF4: SRCCLKREQ9B# NF6: USB_C_GPP_A12] * ==> WWAN_PWR_EN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_A12, 1, LOCK_CONFIG), /* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_H23, 1, LOCK_CONFIG), + /* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_FCPO_L */ + PAD_CFG_GPO_LOCK(GPP_F21, 1, LOCK_CONFIG), /* GPP_H19 : SRCCLKREQ4_L ==> SAR1_INT_L */ PAD_CFG_GPI_APIC_LOCK(GPP_H19, NONE, LEVEL, NONE, LOCK_CONFIG), @@ -112,13 +112,15 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_H23, 0, DEEP), /* * GPP_A12 : [NF1: SATAXPCIE1 NF2: SATAGP1 NF4: SRCCLKREQ9B# NF6: USB_C_GPP_A12] * ==> WWAN_PWR_EN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_A12, 1, LOCK_CONFIG), + /* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_H23, 0, LOCK_CONFIG), + /* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_FCPO_L */ + PAD_CFG_GPO_LOCK(GPP_F21, 0, LOCK_CONFIG), /* * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -183,6 +185,16 @@ /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 0, DEEP), + /* + * GPP_A12 : [NF1: SATAXPCIE1 NF2: SATAGP1 NF4: SRCCLKREQ9B# NF6: USB_C_GPP_A12] + * ==> WWAN_PWR_EN + */ + PAD_CFG_GPO_LOCK(GPP_A12, 1, LOCK_CONFIG), + /* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_H23, 0, LOCK_CONFIG), + /* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_FCPO_L */ + PAD_CFG_GPO_LOCK(GPP_F21, 1, LOCK_CONFIG), + /* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */ PAD_CFG_GPI(GPP_E15, NONE, PLTRST), /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7aa3e7a172143ff1cebea7f48bda45d4fb2c77f7 Gerrit-Change-Number: 84413 Gerrit-PatchSet: 6 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: tree: Explicitly include static.h if referencing static devices
by Nicholas Chin (Code Review) 30 Sep '24

30 Sep '24

Nicholas Chin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/84591?usp=email ) Change subject: tree: Explicitly include static.h if referencing static devices ...................................................................... tree: Explicitly include static.h if referencing static devices As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Add static.h to the includes of files that directly access static devicetree devices in static_devices.h. Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/northbridge/intel/gm45/northbridge.c M src/soc/intel/common/block/systemagent/systemagent.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/84591/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3 Gerrit-Change-Number: 84591 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XS] Change in coreboot[main]: tree: Explicitly include static.h for accessing __pci_* entries
by Nicholas Chin (Code Review) 30 Sep '24

30 Sep '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84591?usp=email ) Change subject: tree: Explicitly include static.h for accessing __pci_* entries ...................................................................... tree: Explicitly include static.h for accessing __pci_* entries As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Add static.h to the includes of files that directly access static devicetree devices in static_devices.h. Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/northbridge/intel/gm45/northbridge.c M src/soc/intel/common/block/systemagent/systemagent.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/84591/1 diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 76ca4ee..f21672e 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -13,6 +13,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <static.h> #include <stdint.h> #include "chip.h" diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 3b71633..0fac07f 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -15,6 +15,7 @@ #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> #include "systemagent_def.h" diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 0adc1b9..9c26e2c 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -21,6 +21,7 @@ #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rcba_pirq.h> +#include <static.h> #define NMI_OFF 0 diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 0a3e26f..a955dfe 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -22,6 +22,7 @@ #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rcba_pirq.h> +#include <static.h> #define NMI_OFF 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/84591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3 Gerrit-Change-Number: 84591 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XS] Change in coreboot[main]: nb/intel/*: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Angel Pons. Hello Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84585?usp=email to look at the new patch set (#2). Change subject: nb/intel/*: Explicitly include static.h for config_of_soc ...................................................................... nb/intel/*: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: Iac8063d2021af83203be8a10b2962c9fb3dd106a Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/northbridge/intel/haswell/broadwell_mrc/raminit.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/raminit_native.c 7 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/84585/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac8063d2021af83203be8a10b2962c9fb3dd106a Gerrit-Change-Number: 84585 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 30 Sep '24

30 Sep '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84589?usp=email ) Change subject: vc/amd/opensil/genoa_poc: Explicitly include static.h for config_of_soc ...................................................................... vc/amd/opensil/genoa_poc: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I83c3e5db85b98196c465146ba8e3481041d2f7eb Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/vendorcode/amd/opensil/genoa_poc/ramstage.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/84589/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c index b18ccc9..b1bbc07 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c @@ -9,6 +9,7 @@ #include <cpu/cpu.h> #include <device/device.h> #include <soc/soc_chip.h> +#include <static.h> #include <stdio.h> #include <xSIM-api.h> #include "opensil_console.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/84589?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I83c3e5db85b98196c465146ba8e3481041d2f7eb Gerrit-Change-Number: 84589 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: mb/*: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Angel Pons, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Patrick Rudolph, Sean Rhodes. Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84588?usp=email ) Change subject: mb/*: Explicitly include static.h for config_of_soc ...................................................................... mb/*: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: Ia793666fda47678764fd33891fddb4aecf207bd4 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c M src/mainboard/amd/mandolin/mainboard.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/puff/variants/baseboard/mainboard.c M src/mainboard/intel/adlrvp/ramstage.c M src/mainboard/lattepanda/mu/ramstage.c M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c M src/mainboard/starlabs/lite/devtree.c M src/mainboard/starlabs/starbook/variants/adl/devtree.c M src/mainboard/starlabs/starbook/variants/cml/devtree.c M src/mainboard/starlabs/starbook/variants/kbl/devtree.c M src/mainboard/starlabs/starbook/variants/rpl/devtree.c M src/mainboard/starlabs/starbook/variants/tgl/devtree.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c 19 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/84588/1 diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c index 7af66e6..11d3a60 100644 --- a/src/mainboard/amd/bilby/mainboard.c +++ b/src/mainboard/amd/bilby/mainboard.c @@ -10,6 +10,7 @@ #include <soc/southbridge.h> #include <soc/pci_devs.h> #include <soc/platform_descriptors.h> +#include <static.h> #include <types.h> #include <commonlib/helpers.h> #include <soc/amd/picasso/chip.h> diff --git a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c index f0060b8..2640e74 100644 --- a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c +++ b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c @@ -3,6 +3,7 @@ #include <device/device.h> #include <soc/amd/phoenix/chip.h> #include <soc/soc_util.h> +#include <static.h> #include <vendorcode/amd/opensil/chip/mpio/chip.h> #include "display_card_type.h" #include "update_devicetree.h" diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index 7975c10..c044a81 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -8,6 +8,7 @@ #include <soc/cpu.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> +#include <static.h> #include <types.h> #include <commonlib/helpers.h> #include <soc/amd/picasso/chip.h> diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index aae4155..a668412 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -11,6 +11,7 @@ #include <ec/ec.h> #include <security/tpm/tss.h> #include <soc/soc_chip.h> +#include <static.h> #include <timer.h> #include <vb2_api.h> diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 795d96e..e908b9e 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -14,6 +14,7 @@ #include <smbios.h> #include <soc/pci_devs.h> #include <soc/nhlt.h> +#include <static.h> #include <stdio.h> #include <timer.h> diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 7bdfb5e..c5ee5b9 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -13,6 +13,7 @@ #include <intelblocks/power_limit.h> #include <smbios.h> #include <soc/ramstage.h> +#include <static.h> #include <stdio.h> #include <variant/sku.h> #include <gpio.h> diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index b77513b..02f861f 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include <smbios.h> +#include <static.h> #include <stdio.h> #include <variant/sku.h> diff --git a/src/mainboard/google/puff/variants/baseboard/mainboard.c b/src/mainboard/google/puff/variants/baseboard/mainboard.c index e0c3440..b455c6d 100644 --- a/src/mainboard/google/puff/variants/baseboard/mainboard.c +++ b/src/mainboard/google/puff/variants/baseboard/mainboard.c @@ -12,6 +12,7 @@ #include <gpio.h> #include <intelblocks/power_limit.h> #include <soc/pci_devs.h> +#include <static.h> #include <timer.h> #define GPIO_HDMI_HPD GPP_E13 diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 3bdc230..fd8e203 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -8,6 +8,7 @@ #include <soc/gpio_soc_defs.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <static.h> #include <string.h> #include <drivers/intel/dptf/chip.h> #include "board_id.h" diff --git a/src/mainboard/lattepanda/mu/ramstage.c b/src/mainboard/lattepanda/mu/ramstage.c index 952524e..e10b179 100644 --- a/src/mainboard/lattepanda/mu/ramstage.c +++ b/src/mainboard/lattepanda/mu/ramstage.c @@ -8,6 +8,7 @@ #include <soc/gpio_soc_defs.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <static.h> #include <string.h> #include <drivers/intel/dptf/chip.h> #include <intelblocks/power_limit.h> diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index 6d0da8d..4ae8454 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -16,6 +16,7 @@ #include <intelblocks/pmclib.h> #include <smbios.h> #include <soc/pm.h> +#include <static.h> #include <stdio.h> #include <string.h> #include <types.h> diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c index 96e0b93..e236c45 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <option.h> +#include <static.h> #include <types.h> #include <variants.h> diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c index d3f8100..f258804 100644 --- a/src/mainboard/starlabs/lite/devtree.c +++ b/src/mainboard/starlabs/lite/devtree.c @@ -4,6 +4,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <option.h> +#include <static.h> #include <types.h> #include <variants.h> diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c index 27ab6c9..60367d0 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <option.h> +#include <static.h> #include <types.h> #include <variants.h> diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c index 95a5d44..20b3b17 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <option.h> +#include <static.h> #include <types.h> #include <variants.h> diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c index 38017dc..b6ff153 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <option.h> +#include <static.h> #include <types.h> #include <variants.h> diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c index b190865..79d8a28 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <option.h> +#include <static.h> #include <types.h> #include <variants.h> diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c index 7c94430..f81a151 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <option.h> +#include <static.h> #include <types.h> #include <variants.h> diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c index b07fc4c..aa0c1bc 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <option.h> +#include <static.h> #include <types.h> #include <variants.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/84588?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia793666fda47678764fd33891fddb4aecf207bd4 Gerrit-Change-Number: 84588 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit September 2024