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Change subject: arch/arm: Build test all arm targets with clang
......................................................................
arch/arm: Build test all arm targets with clang
Some targets cannot be supported by clang as clang generates slightly
larger binaries which the hardware won't accept.
Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/arm/Kconfig
M src/soc/qualcomm/ipq40xx/Kconfig
M src/soc/qualcomm/ipq806x/Kconfig
M src/soc/rockchip/rk3288/Kconfig
4 files changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69747/23
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Change subject: Kconfig: Reverse ARCH_SUPPORTS_CLANG
......................................................................
Kconfig: Reverse ARCH_SUPPORTS_CLANG
Since most targets support clang it's easier to reverse the semantics of
the Kconfig options.
Change-Id: Ib28e7a4cb286b9f8b05be94dae3947179f43c746
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/arm/Kconfig
M src/arch/arm64/Kconfig
M src/arch/ppc64/Kconfig
M src/arch/riscv/Kconfig
M src/arch/x86/Kconfig
6 files changed, 7 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/81659/2
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Hello Martin L Roth, Paul Menzel, build bot (Jenkins),
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Change subject: soc/ti/am335x: Change and optimize memlayout
......................................................................
soc/ti/am335x: Change and optimize memlayout
Clang builds (bootblock: 20800 bytes) are slightly larger than GCC
builds (bootblock: 18688 bytes) so increase the size of both bootblock
and romstage.
The technical reference manual mentions no upper limit to the size of
the bootblock in the TI header so increasing the bootblock size is
allowed.
To be able to link the clang bootblock increase it from 20K to 22K.
Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/ti/beaglebone/board.fmd
M src/soc/ti/am335x/memlayout.ld
2 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/70160/6
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Simon Yang has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/82682?usp=email )
Change subject: mb/google/nissa: Add Vccin Aux Imon Iccmax setting to devicetree
......................................................................
Set Ready For Review
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Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83722?usp=email )
Change subject: mb/google/brya/var/orisa: Remove mux references from typec port
......................................................................
mb/google/brya/var/orisa: Remove mux references from typec port
The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.
BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.
Change-Id: I4a24fb69ebec87f65b679cde0e4a1a8827cd365d
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/orisa/overridetree.cb
1 file changed, 0 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83722/1
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb
index 0a58b3d..3d489c5 100644
--- a/src/mainboard/google/brya/variants/orisa/overridetree.cb
+++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb
@@ -519,20 +519,10 @@
device ref uart0 on end
device ref pch_espi on
chip ec/google/chromeec
- use conn0 as mux_conn[0]
device pnp 0c09.0 on end
end
end
device ref pmc hidden
- chip drivers/intel/pmc_mux
- device generic 0 on
- chip drivers/intel/pmc_mux/conn
- use usb2_port5 as usb2_port
- use tcss_usb3_port1 as usb3_port
- device generic 0 alias conn0 on end
- end
- end
- end
end
device ref hda on
chip drivers/sof
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Change subject: mb/google/nissa: Add Vccin Aux Imon Iccmax setting to devicetree
......................................................................
mb/google/nissa: Add Vccin Aux Imon Iccmax setting to devicetree
According to RDC#646929 Power Map, there are two expected values of
VccInAuxImonIccImax and the value has to align with HW design.
But in current code, vccin_aux_imon_iccmax hard code to 27000(27A),
hence, provide a register in devicetree for projects modification.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Modify the register and confrm the value changed
Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657
Signed-off-by: Simon Yang <simon1.yang(a)intel.com>
---
M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
4 files changed, 15 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/82682/6
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Pranava Y N has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/83707?usp=email )
Change subject: mb/google/brya/var/nova: Remove USB Type-C port setting
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/nova/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83707/comment/ec98d629_4d330920?us… :
PS2, Line 282: register "desc" = ""USB2 Type-C Port C0 (MLB)""
: register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
: register "use_custom_pld" = "true"
: register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 0))"
> I would still call this as USB-C as per product spec […]
Acknowledged
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Derek Huang has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/82682?usp=email )
Change subject: mb/google/nissa: Add Vccin Aux Imon Iccmax setting to devicetree
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82682/comment/850e1aec_c74fea58?us… :
PS4, Line 96: # Vccin Aux Imon Iccmax
: register "vccin_aux_imon_iccmax" = "27000" # 27A
We also need this for trulo. What is the default value of `VccInAuxImonIccImax` if we don't have `vccin_aux_imon_iccmax` configured in the device tree?
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Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83721?usp=email )
Change subject: i2c/drivers/generic: Return ROTM in a package
......................................................................
Set Ready For Review
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