coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/brya/var/nova: Remove USB Type-C port setting
by Pranava Y N (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83707?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brya/var/nova: Remove USB Type-C port setting ...................................................................... mb/google/brya/var/nova: Remove USB Type-C port setting Update the devicetree to remove USB Type-C port related setting as the design doesn't include a USB-C port. BUG=b:348332200 TEST=Able to build google/nova Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/nova/overridetree.cb 1 file changed, 10 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83707/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Gerrit-Change-Number: 83707 Gerrit-PatchSet: 3 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/riven: Disable CNVi WIFI and BT based on fw_config
by David Wu (Code Review) 01 Aug '24

01 Aug '24

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83720?usp=email ) Change subject: mb/google/nissa/var/riven: Disable CNVi WIFI and BT based on fw_config ...................................................................... mb/google/nissa/var/riven: Disable CNVi WIFI and BT based on fw_config Disable CNVi WIFI and BT based on fw_config. BUG=b:337169542 TEST=Dut boots fine with both Wifi6e & Wifi7 based cbi settings. Change-Id: Icb925c02c73d3630be8b78debf608270b08854fe Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/riven/fw_config.c M src/mainboard/google/brya/variants/riven/overridetree.cb 2 files changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/83720/1 diff --git a/src/mainboard/google/brya/variants/riven/fw_config.c b/src/mainboard/google/brya/variants/riven/fw_config.c index b22463f..96fc781 100644 --- a/src/mainboard/google/brya/variants/riven/fw_config.c +++ b/src/mainboard/google/brya/variants/riven/fw_config.c @@ -65,6 +65,16 @@ PAD_NC(GPP_I18, NONE), }; +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (!fw_config_probe(FW_CONFIG(WIFI_TYPE, WIFI_CNVI))) { + printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); + config->cnvi_bt_core = false; + printk(BIOS_INFO, "CNVi bluetooth audio offload disabled by fw_config\n"); + config->cnvi_bt_audio_offload = false; + } +} + void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { if (!fw_config_is_provisioned()) { diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb index 301d72a..044d411 100644 --- a/src/mainboard/google/brya/variants/riven/overridetree.cb +++ b/src/mainboard/google/brya/variants/riven/overridetree.cb @@ -230,11 +230,10 @@ probe WFC WFC_MIPI_OVTI8856 end device ref cnvi_wifi on + probe WIFI_TYPE WIFI_CNVI chip drivers/wifi/generic register "enable_cnvi_ddr_rfim" = "true" - device generic 0 on - probe WIFI_TYPE WIFI_CNVI - end + device generic 0 on end end end device ref i2c1 on -- To view, visit https://review.coreboot.org/c/coreboot/+/83720?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb925c02c73d3630be8b78debf608270b08854fe Gerrit-Change-Number: 83720 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com>

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: KunYi Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83719?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... mb/lattepanda: Add support for LattePanda Mu Add initial support for the LattePanda Mu board, which features: Intel Alder Lake-N N100 processor 8GB LPDDR5 memory 64GB eMMC storage SO-DIMM 260-pin connector for function expansion This commit includes: Basic board configuration Memory initialization Essential I/O setup TODO: Verify and fine-tune ACPI tables Test and optimize power management Implement advanced features specific to this board Testing with Lite carrier board Booting into default installed Windows: Passed Installing Ubuntu 22.04: Failed (system shuts down, unable to auto-reboot) USB 3.0/2.0: Working HDMI output: Working S3 sleep mode: Failed Power on after shutdown: Failed (requires power removal) Ethernet port: Not working UART of SuperIO in OS: Missing Environment Controller: Not supported Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com> --- A configs/config.lattepanda_mu A src/mainboard/lattepanda/Kconfig A src/mainboard/lattepanda/Kconfig.name A src/mainboard/lattepanda/mu/Kconfig A src/mainboard/lattepanda/mu/Kconfig.name A src/mainboard/lattepanda/mu/Makefile.mk A src/mainboard/lattepanda/mu/board_info.txt A src/mainboard/lattepanda/mu/bootblock.c A src/mainboard/lattepanda/mu/data.vbt A src/mainboard/lattepanda/mu/devicetree.cb A src/mainboard/lattepanda/mu/dsdt.asl A src/mainboard/lattepanda/mu/gpio.c A src/mainboard/lattepanda/mu/include/baseboard/gpio.h A src/mainboard/lattepanda/mu/include/baseboard/variants.h A src/mainboard/lattepanda/mu/mainboard.c A src/mainboard/lattepanda/mu/memory.c A src/mainboard/lattepanda/mu/ramstage.c A src/mainboard/lattepanda/mu/romstage_fsp_params.c A src/mainboard/lattepanda/mu/smihandler.c A src/mainboard/lattepanda/mu/spd/Makefile.mk A src/mainboard/lattepanda/mu/spd/empty.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex 23 files changed, 902 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83719/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 2 Gerrit-Owner: KunYi Chen Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: KunYi Chen

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[M] Change in coreboot[main]: mb/google/skyrim: Combine the function port_descriptors for variants
by Bao Zheng (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Jason Nien, Jon Murphy, Martin Roth, Matt DeVillier, Matt DeVillier, Paul Menzel, Zheng Bao. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/83646?usp=email ) Change subject: mb/google/skyrim: Combine the function port_descriptors for variants ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83646/comment/c46bf726_2d6cd197?us… : PS1, Line 8: > Please elaborate. Done https://review.coreboot.org/c/coreboot/+/83646/comment/a28ec220_1390c505?us… : PS1, Line 9: BUG=b:346716300 > I don't understand how this change relates to this bug Done File src/mainboard/google/skyrim/variants/baseboard/port_descriptors_combo.c: PS1: > Agree that having duplicate code is not a good thing. I am a little hesitant about this change. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Gerrit-Change-Number: 83646 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Aug 2024 07:15:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com>

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[M] Change in coreboot[main]: mb/google/skyrim: Combine the function port_descriptors for variants
by Bao Zheng (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Bao Zheng, Jason Nien, Martin Roth, Matt DeVillier, Matt DeVillier, Zheng Bao. Hello Jason Nien, Martin Roth, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83646?usp=email to look at the new patch set (#5). Change subject: mb/google/skyrim: Combine the function port_descriptors for variants ...................................................................... mb/google/skyrim: Combine the function port_descriptors for variants Remove the weak function. Combine all the getting descriptors together. BUG=b:279144932 TEST=Build Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/port_descriptors.h M src/mainboard/google/skyrim/variants/baseboard/port_descriptors.c M src/mainboard/google/skyrim/variants/markarth/Makefile.mk D src/mainboard/google/skyrim/variants/markarth/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/Makefile.mk D src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 6 files changed, 45 insertions(+), 117 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83646/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/83646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Gerrit-Change-Number: 83646 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 01 Aug '24

01 Aug '24

KunYi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83719?usp=email ) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... mb/lattepanda: Add support for LattePanda Mu Add initial support for the LattePanda Mu board, which features: Intel Alder Lake-N N100 processor 8GB LPDDR5 memory 64GB eMMC storage SO-DIMM 260-pin connector for function expansion This commit includes: Basic board configuration Memory initialization Essential I/O setup TODO: Verify and fine-tune ACPI tables Test and optimize power management Implement advanced features specific to this board Testing with Lite carrier board Booting into default installed Windows: Passed Installing Ubuntu 22.04: Failed (system shuts down, unable to auto-reboot) USB 3.0/2.0: Working HDMI output: Working S3 sleep mode: Failed Power on after shutdown: Failed (requires power removal) Ethernet port: Not working UART of SuperIO in OS: Missing Environment Controller: Not supported Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com> --- A configs/config.lattepanda_mu A src/mainboard/lattepanda/Kconfig A src/mainboard/lattepanda/Kconfig.name A src/mainboard/lattepanda/mu/Kconfig A src/mainboard/lattepanda/mu/Kconfig.name A src/mainboard/lattepanda/mu/Makefile.mk A src/mainboard/lattepanda/mu/board_info.txt A src/mainboard/lattepanda/mu/bootblock.c A src/mainboard/lattepanda/mu/data.vbt A src/mainboard/lattepanda/mu/devicetree.cb A src/mainboard/lattepanda/mu/dsdt.asl A src/mainboard/lattepanda/mu/gpio.c A src/mainboard/lattepanda/mu/include/baseboard/gpio.h A src/mainboard/lattepanda/mu/include/baseboard/variants.h A src/mainboard/lattepanda/mu/mainboard.c A src/mainboard/lattepanda/mu/memory.c A src/mainboard/lattepanda/mu/ramstage.c A src/mainboard/lattepanda/mu/romstage_fsp_params.c A src/mainboard/lattepanda/mu/smihandler.c A src/mainboard/lattepanda/mu/spd/Makefile.mk A src/mainboard/lattepanda/mu/spd/empty.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex 23 files changed, 904 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83719/1 diff --git a/configs/config.lattepanda_mu b/configs/config.lattepanda_mu new file mode 100644 index 0000000..96f3de1 --- /dev/null +++ b/configs/config.lattepanda_mu @@ -0,0 +1,11 @@ +CONFIG_VENDOR_LATTEPANDA=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_FSP_FD_PATH="3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y diff --git a/src/mainboard/lattepanda/Kconfig b/src/mainboard/lattepanda/Kconfig new file mode 100644 index 0000000..f1e240f --- /dev/null +++ b/src/mainboard/lattepanda/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_LATTEPANDA + +choice + prompt "Mainboard model" + +source "src/mainboard/lattepanda/*/Kconfig.name" + +endchoice + +source "src/mainboard/lattepanda/*/Kconfig" + +config MAINBOARD_VENDOR + default "LattePanda" + +endif # VENDOR_LATTEPANDA diff --git a/src/mainboard/lattepanda/Kconfig.name b/src/mainboard/lattepanda/Kconfig.name new file mode 100644 index 0000000..f720c6e --- /dev/null +++ b/src/mainboard/lattepanda/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_LATTEPANDA + bool "LattePanda" diff --git a/src/mainboard/lattepanda/mu/Kconfig b/src/mainboard/lattepanda/mu/Kconfig new file mode 100644 index 0000000..c9f6917 --- /dev/null +++ b/src/mainboard/lattepanda/mu/Kconfig @@ -0,0 +1,39 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_LATTEPANDA_MU + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF + select DRIVERS_INTEL_MIPI_CAMERA + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_ALDERLAKE_PCH_N + select SUPERIO_ITE_IT8613E + select INTEL_GMA_HAVE_VBT + +config MAINBOARD_DIR + default "lattepanda/mu" + +config MAINBOARD_PART_NUMBER + default "MU_8G" + +config UART_FOR_CONSOLE + int + default 0 + +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/lattepanda/mu/Kconfig.name b/src/mainboard/lattepanda/mu/Kconfig.name new file mode 100644 index 0000000..3111b34 --- /dev/null +++ b/src/mainboard/lattepanda/mu/Kconfig.name @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_LATTEPANDA_MU + bool "LattePanda Mu" + help + This mainboard code along with the example/min86 SoC + should serve as a minimal example how a buildable x86 SoC code + base can look like. + + This can serve, for instance, as a basis to add new SoCs to + coreboot. Starting with a buildable commit should help with + the review of the actual code, and also avoid any regressions + when common coreboot code changes. diff --git a/src/mainboard/lattepanda/mu/Makefile.mk b/src/mainboard/lattepanda/mu/Makefile.mk new file mode 100644 index 0000000..470f55b --- /dev/null +++ b/src/mainboard/lattepanda/mu/Makefile.mk @@ -0,0 +1,16 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c +romstage-y += memory.c + +ramstage-y += mainboard.c +ramstage-y += gpio.c +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + + diff --git a/src/mainboard/lattepanda/mu/board_info.txt b/src/mainboard/lattepanda/mu/board_info.txt new file mode 100644 index 0000000..b1d0e97 --- /dev/null +++ b/src/mainboard/lattepanda/mu/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: DFRobot +Board name: LattePanda Mu +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/lattepanda/mu/bootblock.c b/src/mainboard/lattepanda/mu/bootblock.c new file mode 100644 index 0000000..11bd669 --- /dev/null +++ b/src/mainboard/lattepanda/mu/bootblock.c @@ -0,0 +1,20 @@ + +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x29, 0xc1); + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/lattepanda/mu/data.vbt b/src/mainboard/lattepanda/mu/data.vbt new file mode 100644 index 0000000..fc35e8f --- /dev/null +++ b/src/mainboard/lattepanda/mu/data.vbt Binary files differ diff --git a/src/mainboard/lattepanda/mu/devicetree.cb b/src/mainboard/lattepanda/mu/devicetree.cb new file mode 100644 index 0000000..bfd3152 --- /dev/null +++ b/src/mainboard/lattepanda/mu/devicetree.cb @@ -0,0 +1,283 @@ + +chip soc/intel/alderlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + # Sagv Configuration + register "sagv" = "SaGv_Enabled" + + # Enable DPTF + register "dptf_enable" = "1" + + # eMMC HS400 + register "emmc_enable_hs400_mode" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port3 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type A/ M.2 WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # Enable PCH PCIE RP 7 using CLK 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 9 using CLK 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + register "sata_salp_support" = "0" + + # Enable EDP in PortA + register "ddi_portA_config" = "1" + # Enable HDMI in Port B + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + # TCSS USB3 + register "tcss_aux_ori" = "4" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}" + + register "s0ix_enable" = "1" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "serial_io_gspi_cs_mode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "serial_io_gspi_cs_state" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + device domain 0 on + device ref igpu on end + device ref dtt on + chip drivers/intel/dptf + + ## sensor information + register "options.tsr[0].desc" = ""Ambient"" + register "options.tsr[1].desc" = ""Battery"" + register "options.tsr[2].desc" = ""DDR"" + register "options.tsr[3].desc" = ""Skin"" + register "options.tsr[4].desc" = ""VR"" + + ## Active Policy + # TODO: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 90), + TEMP_PCT(90, 80), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(80, 90), + TEMP_PCT(70, 80), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000), + [5] = DPTF_PASSIVE(CPU, TEMP_SENSOR_4, 85, 50000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN), + [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 95, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 25000, + .max_power = 35000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref ipu off end + device ref crashlog off end + device ref tcss_xhci on end + device ref xhci on end + device ref cnvi_wifi on end + device ref i2c0 on end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata off end + device ref i2c5 off end + device ref pcie_rp7 on end + device ref pcie_rp9 on end + device ref uart0 on end + device ref gspi0 on end + device ref p2sb on end + device ref emmc on end + device ref ish on end + device ref ufs on end + device ref hda on end + device ref smbus on end + device ref pch_espi on + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c03f1" + register "gen4_dec" = "0x000c0081" + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + end +end diff --git a/src/mainboard/lattepanda/mu/dsdt.asl b/src/mainboard/lattepanda/mu/dsdt.asl new file mode 100644 index 0000000..a3a29bc --- /dev/null +++ b/src/mainboard/lattepanda/mu/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <baseboard/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lattepanda/mu/gpio.c b/src/mainboard/lattepanda/mu/gpio.c new file mode 100644 index 0000000..e39da35 --- /dev/null +++ b/src/mainboard/lattepanda/mu/gpio.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* ESPI_IO0_EC_R / ESPI_IO0_HDR */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + /* ESPI_IO1_EC_R / ESPI_IO1_HDR */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + /* ESPI_IO2_EC_R / ESPI_IO2_HDR */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + /* ESPI_IO3_EC_R / ESPI_IO3_HDR */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + /* ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + /* ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + /* ESPI_CLK_EC_R / ESPI_CLK_HDR */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* ESPI_RST_EC_R_N / ESPI_RST_HDR_N */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* I5 : NC */ + PAD_NC(GPP_I5, NONE), + /* I7 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + /* I8 : EMMC_DATA0 ==> EMMC_D0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + /* I9 : EMMC_DATA1 ==> EMMC_D1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + /* I10 : EMMC_DATA2 ==> EMMC_D2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + /* I11 : EMMC_DATA3 ==> EMMC_D3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + /* I12 : EMMC_DATA4 ==> EMMC_D4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + /* I13 : EMMC_DATA5 ==> EMMC_D5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + /* I14 : EMMC_DATA6 ==> EMMC_D6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + /* I15 : EMMC_DATA7 ==> EMMC_D7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + /* I16 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + /* I17 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + /* I18 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* EDP1_HPD_MIPI_PNL_RST */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* PM_SLP_DRAM_N */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), + /* CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* DDIB_DP_HDMI_ALS_HDP */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/lattepanda/mu/include/baseboard/gpio.h b/src/mainboard/lattepanda/mu/include/baseboard/gpio.h new file mode 100644 index 0000000..d809145 --- /dev/null +++ b/src/mainboard/lattepanda/mu/include/baseboard/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/lattepanda/mu/include/baseboard/variants.h b/src/mainboard/lattepanda/mu/include/baseboard/variants.h new file mode 100644 index 0000000..61b0f68 --- /dev/null +++ b/src/mainboard/lattepanda/mu/include/baseboard/variants.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stdint.h> + +/* Functions to configure GPIO as per variant schematics */ +void variant_configure_gpio_pads(void); +void variant_configure_early_gpio_pads(void); + +size_t variant_memory_sku(void); +const struct mb_cfg *variant_memory_params(void); +void rpl_memory_params(FSPM_UPD *memupd); + +/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); +struct cpu_power_limits { + uint16_t mchid; + u8 cpu_tdp; + unsigned int pl1_min_power; + unsigned int pl1_max_power; + unsigned int pl2_min_power; + unsigned int pl2_max_power; + unsigned int pl4_power; +}; +/* Modify Power Limit devictree settings during ramstage */ +void variant_update_power_limits(void); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/lattepanda/mu/mainboard.c b/src/mainboard/lattepanda/mu/mainboard.c new file mode 100644 index 0000000..225ff16 --- /dev/null +++ b/src/mainboard/lattepanda/mu/mainboard.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <cpu/cpu.h> +#include <cpu/intel/cpu_ids.h> +#include <device/device.h> +#include <drivers/intel/gma/opregion.h> +#include <fw_config.h> +#include <smbios.h> +#include <soc/gpio.h> +#include <stdint.h> +#include <stdio.h> + +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; + uint8_t sku_id = 1; + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} + +static void mainboard_init(void *chip_info) +{ + variant_configure_gpio_pads(); + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + + +static void mainboard_enable(struct device *dev) +{ + +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; + +const char *mainboard_vbt_filename(void) +{ + return "vbt.bin"; +} diff --git a/src/mainboard/lattepanda/mu/memory.c b/src/mainboard/lattepanda/mu/memory.c new file mode 100644 index 0000000..e6c8179 --- /dev/null +++ b/src/mainboard/lattepanda/mu/memory.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <soc/romstage.h> + +static const struct mb_cfg mu_lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 10, 9, 11, 15, 14, 8, 13 }, + .dq1 = { 0, 3, 1, 2, 7, 4, 6, 5 }, + }, + .ddr1 = { + .dq0 = { 0, 2, 1, 3, 4, 7, 5, 6 }, + .dq1 = { 13, 11, 9, 10, 8, 15, 12, 14 }, + }, + .ddr2 = { + .dq0 = { 0, 1, 2, 3, 7, 4, 5, 6 }, + .dq1 = { 9, 10, 8, 11, 14, 15, 12, 13 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 14, 10, 8, 11, 12, 15, 9, 13 }, + }, + .ddr4 = { + .dq0 = { 3, 0, 2, 1, 6, 7, 5, 4 }, + .dq1 = { 12, 14, 15, 13, 9, 11, 8, 10 }, + }, + .ddr5 = { + .dq0 = { 0, 1, 2, 3, 6, 4, 5, 7 }, + .dq1 = { 15, 14, 12, 13, 9, 11, 8, 10 }, + }, + .ddr6 = { + .dq0 = { 3, 0, 1, 2, 5, 4, 6, 7 }, + .dq1 = { 12, 13, 15, 14, 9, 11, 10, 8 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 2, 1, 5, 4, 6, 7 }, + .dq1 = { 10, 8, 15, 14, 9, 12, 13, 11 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, + + .LpDdrDqDqsReTraining = 1, + + .lp5x_config = { + .ccc_config = 0x00, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &mu_lp5_mem_config; +} diff --git a/src/mainboard/lattepanda/mu/ramstage.c b/src/mainboard/lattepanda/mu/ramstage.c new file mode 100644 index 0000000..64f3785 --- /dev/null +++ b/src/mainboard/lattepanda/mu/ramstage.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <soc/gpio_soc_defs.h> +#include <soc/pci_devs.h> +#include <soc/soc_chip.h> +#include <string.h> +#include <drivers/intel/dptf/chip.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, PL4 */ + /* PL2 values are for performance configuration */ + { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000, 140000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000, 140000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 }, + { PCI_DID_INTEL_ADL_N_ID_1, 15, 3000, 15000, 35000, 35000, 83000 }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_4, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, 3000, 6000, 25000, 25000, 78000 }, +}; + +WEAK_DEV_PTR(dptf_policy); +void variant_update_power_limits(void) +{ + const struct device *policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = config_of(policy_dev); + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + u8 tdp = get_cpu_tdp(); + + for (size_t i = 0; i < ARRAY_SIZE(limits); i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + struct dptf_power_limits *settings = &config->controls.power_limits; + config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config = conf->power_limits_config; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + MILLIWATTS_TO_WATTS); + printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power, + limits[i].pl4_power); + } + } +} + +void variant_devtree_update(void) +{ + variant_update_power_limits(); +} diff --git a/src/mainboard/lattepanda/mu/romstage_fsp_params.c b/src/mainboard/lattepanda/mu/romstage_fsp_params.c new file mode 100644 index 0000000..73f8cc2 --- /dev/null +++ b/src/mainboard/lattepanda/mu/romstage_fsp_params.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <soc/meminit.h> +#include <baseboard/variants.h> + +static size_t get_spd_index(void) +{ + size_t spd_index = 0; + printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index); + return spd_index; +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct mb_cfg *mem_config = variant_memory_params(); + /* + * Alder Lake common meminit block driver considers bus width to be 128-bit and + * populates the meminit data accordingly. Alder Lake-N has single memory controller + * with 64-bit bus width. By setting half_populated to true, only the bottom half is + * populated. + * TODO: Implement __weak variant_is_half_populated(void) function. + */ + const bool half_populated = (true); + + const struct mem_spd memory_down_spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = get_spd_index(), + }; + + memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated); +} diff --git a/src/mainboard/lattepanda/mu/smihandler.c b/src/mainboard/lattepanda/mu/smihandler.c new file mode 100644 index 0000000..a3e0999 --- /dev/null +++ b/src/mainboard/lattepanda/mu/smihandler.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> +#include <intelblocks/smihandler.h> + +void mainboard_smi_espi_handler(void) +{ + return; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + return; +} + +int mainboard_smi_apmc(u8 apmc) +{ + return 0; +} diff --git a/src/mainboard/lattepanda/mu/spd/Makefile.mk b/src/mainboard/lattepanda/mu/spd/Makefile.mk new file mode 100644 index 0000000..f165770 --- /dev/null +++ b/src/mainboard/lattepanda/mu/spd/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = mu_lp5_8gb # 0b000 +SPD_SOURCES += empty # 0b001 +SPD_SOURCES += mu_lp5_16gb # 0b002 +SPD_SOURCES += empty # 0b003 +SPD_SOURCES += empty # 0b004 +SPD_SOURCES += empty # 0b005 +SPD_SOURCES += empty # 0b006 +SPD_SOURCES += empty # 0b007 diff --git a/src/mainboard/lattepanda/mu/spd/empty.spd.hex b/src/mainboard/lattepanda/mu/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/lattepanda/mu/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex b/src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex new file mode 100644 index 0000000..d206466 --- /dev/null +++ b/src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex @@ -0,0 +1,32 @@ +27 10 13 0E 16 22 F9 08 00 40 00 00 0A 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex b/src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex new file mode 100644 index 0000000..a8d059c --- /dev/null +++ b/src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex @@ -0,0 +1,32 @@ +27 10 13 0E 16 22 B9 08 00 40 00 00 02 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 1 Gerrit-Owner: KunYi Chen

1 0

[M] Change in coreboot[main]: mb/google/skyrim: Combine the function port_descriptors for variants
by Bao Zheng (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Bao Zheng, Jason Nien, Martin Roth, Matt DeVillier, Matt DeVillier, Zheng Bao. Hello Jason Nien, Martin Roth, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83646?usp=email to look at the new patch set (#4). Change subject: mb/google/skyrim: Combine the function port_descriptors for variants ...................................................................... mb/google/skyrim: Combine the function port_descriptors for variants Remove the weak function. Combine all the getting descriptors together. BUG=b:279144932 TEST=Build Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/port_descriptors.h M src/mainboard/google/skyrim/variants/baseboard/port_descriptors.c M src/mainboard/google/skyrim/variants/markarth/Makefile.mk D src/mainboard/google/skyrim/variants/markarth/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/Makefile.mk D src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 6 files changed, 44 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83646/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Gerrit-Change-Number: 83646 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: mb/google/skyrim: Combine the function port_descriptors for variants
by Bao Zheng (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Bao Zheng, Jason Nien, Martin Roth, Matt DeVillier, Matt DeVillier, Zheng Bao. Hello Jason Nien, Martin Roth, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83646?usp=email to look at the new patch set (#3). Change subject: mb/google/skyrim: Combine the function port_descriptors for variants ...................................................................... mb/google/skyrim: Combine the function port_descriptors for variants Remove the weak function. Combine all the getting decriptors together. BUG=b:279144932 TEST=Build Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/port_descriptors.h M src/mainboard/google/skyrim/variants/baseboard/port_descriptors.c M src/mainboard/google/skyrim/variants/markarth/Makefile.mk D src/mainboard/google/skyrim/variants/markarth/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/Makefile.mk D src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 6 files changed, 44 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83646/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Gerrit-Change-Number: 83646 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

1 0

[XL] Change in coreboot[main]: update FSP headers of ADL-N to latest version
by KunYi Chen (Code Review) 01 Aug '24

01 Aug '24

KunYi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83718?usp=email ) Change subject: update FSP headers of ADL-N to latest version ...................................................................... update FSP headers of ADL-N to latest version IoT ADL-N version update to MR5(5132_00) Change-Id: I96fccbb92866fbc18c57187628612fda655cd7a7 Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h 4 files changed, 2,648 insertions(+), 1,037 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83718/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83718?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I96fccbb92866fbc18c57187628612fda655cd7a7 Gerrit-Change-Number: 83718 Gerrit-PatchSet: 1 Gerrit-Owner: KunYi Chen

1 0

[M] Change in coreboot[main]: mb/google/skyrim: Combine the function port_descriptors for variants
by Bao Zheng (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Bao Zheng, Jason Nien, Martin Roth, Matt DeVillier, Matt DeVillier, Zheng Bao. Hello Jason Nien, Martin Roth, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83646?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/skyrim: Combine the function port_descriptors for variants ...................................................................... mb/google/skyrim: Combine the function port_descriptors for variants Remove the weak function. Combine all the getting decriptors together. BUG=b:346716300 TEST=Build Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/port_descriptors.h M src/mainboard/google/skyrim/variants/baseboard/port_descriptors.c M src/mainboard/google/skyrim/variants/markarth/Makefile.mk D src/mainboard/google/skyrim/variants/markarth/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/Makefile.mk D src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 6 files changed, 44 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83646/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Gerrit-Change-Number: 83646 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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coreboot-gerrit August 2024