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Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83656?usp=email )
Change subject: mb/google/trulo/var/orisa: Update ISH GPIO's configuration
......................................................................
Patch Set 3:
(2 comments)
This change is ready for review.
Patchset:
PS2:
> your patch needs rebasing as the underlying coreboot code had changed since you forked it.
Done
File src/mainboard/google/brya/variants/orisa/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83656/comment/68d25aff_fcd32671?us… :
PS2, Line 527: orisa_ish
> can we have generic name w/o associating any platform ? if you wish to attach a platform name, then […]
i have removed the firmware name config for the Orisa. Just keeping the GPIO's changes in this patch
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83354?usp=email
to look at the new patch set (#33).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,270 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/33
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Change subject: mb/google/dedede/var/awasuki: Enable ELAN touchscreen with fw_config
......................................................................
Patch Set 6: Code-Review+1
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Change subject: mb/google/brox: Create jubilant variant
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Patch Set 30: Code-Review+1
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Change subject: security/vboot: Include new gbb flag to enforce CSE sync
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_refere… is merged. […]
Marking this open.
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Change subject: security/vboot: Include new gbb flag to enforce CSE sync
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_refere… is merged. Please update the vboot submodule by `util/scripts/update_submodules -R ./3rdparty/vboot -c 1`, upload the patch, and rebase this one onto that.
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Change subject: mb/google/dedede/var/awasuki: Enable ELAN touchscreen with fw_config
......................................................................
Patch Set 6:
(3 comments)
File src/mainboard/google/dedede/variants/awasuki/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83704/comment/afe28fb0_96321b9b?us… :
PS5, Line 1: fw_config
: field TOUCH 5
: option TOUCH_ABSENT 0
: option TOUCH_PRESENT 1
: end
: end
> Please move this to variants/baseboard/devicetree.cb along with other fw_config. […]
Done
File src/mainboard/google/dedede/variants/awasuki/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83704/comment/a5f9071d_506f4ee1?us… :
PS5, Line 9: /* H4 : AP_I2C_TS_SDA */
: PAD_NC(GPP_H4, NONE),
: /* H5 : AP_I2C_TS_SCL */
: PAD_NC(GPP_H5, NONE),
> Also you need to configure ENABLE, Reset and Stop/Report GPIOs as NC so that they are not floating o […]
Done
https://review.coreboot.org/c/coreboot/+/83704/comment/9aeb7032_ba580eae?us… :
PS5, Line 24: if (!fw_config_probe(FW_CONFIG(TOUCH, TOUCH_PRESENT))) {
: cfg->SerialIoI2cMode[PchSerialIoIndexI2C2] = PchSerialIoDisabled;
: }
:
: if (!fw_config_probe(FW_CONFIG(TOUCH, TOUCH_PRESENT))) {
: printk(BIOS_INFO, "Disable TS GPIO pins.\n");
: gpio_configure_pads(ts_disable_pad, ARRAY_SIZE(ts_disable_pad));
: }
> Both the if blocks can be combined into one.
Done
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