Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83812?usp=email )
Change subject: util/amdfwtool: add support to specify RPMC NVRAM region
......................................................................
util/amdfwtool: add support to specify RPMC NVRAM region
Add support to specify the base and size of the replay-protected
monotonic counter (RPMC) non-volatile storage area in the SPI flash. A
later patch will use this to tell amdfwtool about the location and size
of the corresponding FMAP section.
This code is ported from
github.com/teslamotors/coreboot/tree/tesla-4.12-amd
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Idafa7d9bf64125bcabd9b47e77147bcffee739e2
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/opts.c
2 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/83812/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 1dac476..1fe9923 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1011,7 +1011,8 @@
pspdir->entries[count].addr = fw_table[i].other;
pspdir->entries[count].address_mode = 0;
count++;
- } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) {
+ } else if (fw_table[i].type == AMD_FW_PSP_NVRAM ||
+ fw_table[i].type == AMD_RPMC_NVRAM) {
if (fw_table[i].filename == NULL) {
if (fw_table[i].size == 0)
continue;
diff --git a/util/amdfwtool/opts.c b/util/amdfwtool/opts.c
index 511ffd0..62bbc97 100644
--- a/util/amdfwtool/opts.c
+++ b/util/amdfwtool/opts.c
@@ -68,6 +68,8 @@
LONGOPT_BIOS_SIG = 259,
LONGOPT_NVRAM_BASE = 260,
LONGOPT_NVRAM_SIZE = 261,
+ LONGOPT_RPMC_NVRAM_BASE = 262,
+ LONGOPT_RPMC_NVRAM_SIZE = 263,
};
static const char optstring[] = {AMDFW_OPT_CONFIG, ':',
@@ -87,6 +89,8 @@
{"nvram", required_argument, 0, AMDFW_OPT_NVRAM },
{"nvram-base", required_argument, 0, LONGOPT_NVRAM_BASE },
{"nvram-size", required_argument, 0, LONGOPT_NVRAM_SIZE },
+ {"rpmc-nvram-base", required_argument, 0, LONGOPT_RPMC_NVRAM_BASE },
+ {"rpmc-nvram-size", required_argument, 0, LONGOPT_RPMC_NVRAM_SIZE },
{"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE },
{"token-unlock", no_argument, 0, AMDFW_OPT_UNLOCK },
{"whitelist", required_argument, 0, AMDFW_OPT_WHITELIST },
@@ -150,6 +154,8 @@
printf("--token-unlock Set token unlock\n");
printf("--nvram-base <HEX_VAL> Base address of nvram\n");
printf("--nvram-size <HEX_VAL> Size of nvram\n");
+ printf("--rpmc-nvram-base <HEX_VAL> Base address of RPMC nvram\n");
+ printf("--rpmc-nvram-size <HEX_VAL> Size of RPMC nvram\n");
printf("--whitelist Set if there is a whitelist\n");
printf("--use-pspsecureos Set if psp secure OS is needed\n");
printf("--load-mp2-fw Set if load MP2 firmware\n");
@@ -577,6 +583,16 @@
register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, 0, optarg);
sub = instance = 0;
break;
+ case LONGOPT_RPMC_NVRAM_BASE:
+ /* PSP RPMC NV base */
+ register_amd_psp_fw_addr(AMD_RPMC_NVRAM, sub, optarg, 0);
+ sub = instance = 0;
+ break;
+ case LONGOPT_RPMC_NVRAM_SIZE:
+ /* PSP RPMC NV size */
+ register_amd_psp_fw_addr(AMD_RPMC_NVRAM, sub, 0, optarg);
+ sub = instance = 0;
+ break;
case AMDFW_OPT_CONFIG:
cb_config->config = optarg;
break;
--
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Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Idafa7d9bf64125bcabd9b47e77147bcffee739e2
Gerrit-Change-Number: 83812
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83778?usp=email )
Change subject: soc/amd/common/psp_smi_flash: add buffer overflow checks
......................................................................
soc/amd/common/psp_smi_flash: add buffer overflow checks
Before 'handle_psp_command' calls any of the functions in this file, it
make sure that the 'size' field in the command buffer's header doesn't
indicate that the command buffer is larger than the SMM memory region
reserved for it.
The read/write command buffer has a 'num_bytes' field to indicate how
many bytes should be read from the SPI flash and put into the data
buffer within the command buffer or how many bytes from this buffer
should be written to the flash. While we should be able to assume that
the PSP won't send us malformed command buffer, we should still better
check this just to be sure.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ib4e8514eedc3ad154a705c8a1e85d367e452dbed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83778
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/common/block/psp/psp_smi_flash.c
1 file changed, 22 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c
index 2d075ef..405fc29 100644
--- a/src/soc/amd/common/block/psp/psp_smi_flash.c
+++ b/src/soc/amd/common/block/psp/psp_smi_flash.c
@@ -104,6 +104,16 @@
*num_blocks = read64(&cmd_buf->req.num_blocks);
}
+static bool is_valid_rw_byte_count(struct mbox_pspv2_cmd_spi_read_write *cmd_buf,
+ u64 num_bytes)
+{
+ const u32 cmd_buf_size = read32(&cmd_buf->header.size);
+ const size_t payload_buffer_offset =
+ offsetof(struct mbox_pspv2_cmd_spi_read_write, req) +
+ offsetof(struct pspv2_spi_read_write_request, buffer);
+ return num_bytes <= cmd_buf_size - payload_buffer_offset;
+}
+
static const char *id_to_region_name(u64 target_nv_id)
{
switch (target_nv_id) {
@@ -238,6 +248,12 @@
get_psp_spi_read_write(cmd_buf, &target_nv_id, &lba, &offset, &num_bytes, &data);
+ if (!is_valid_rw_byte_count(cmd_buf, num_bytes)) {
+ printk(BIOS_ERR, "PSP: Read command requested more bytes than we have space "
+ "for in the buffer\n");
+ return MBOX_PSP_COMMAND_PROCESS_ERROR;
+ }
+
ret = find_psp_spi_flash_device_region(target_nv_id, &store, &flash);
if (ret != MBOX_PSP_SUCCESS)
@@ -281,6 +297,12 @@
get_psp_spi_read_write(cmd_buf, &target_nv_id, &lba, &offset, &num_bytes, &data);
+ if (!is_valid_rw_byte_count(cmd_buf, num_bytes)) {
+ printk(BIOS_ERR, "PSP: Write command contains more bytes than we have space "
+ "for in the buffer\n");
+ return MBOX_PSP_COMMAND_PROCESS_ERROR;
+ }
+
ret = find_psp_spi_flash_device_region(target_nv_id, &store, &flash);
if (ret != MBOX_PSP_SUCCESS)
--
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Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ib4e8514eedc3ad154a705c8a1e85d367e452dbed
Gerrit-Change-Number: 83778
Gerrit-PatchSet: 4
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83776?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/amd/common/psp_smi_flash: implement SPI info command
......................................................................
soc/amd/common/psp_smi_flash: implement SPI info command
Detect the block size of the SPI flash and number of flash blocks
reserved for the flash region corresponding to the 'target_nv_id' field
in the command buffer. This information is then written to the
corresponding fields in the command buffer. Since detecting the flash
chip still might result in accesses to it, make sure that it's available
for use and not currently used by an OS driver. Since this code is
inside the SMI handler, we don't have to worry about this code to be
interrupted, so we don't need to set some bit to tell other code that
we're currently using the SPI controller in the SMI handler.
This patch is a modified version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
Change-Id: I19041a27a9e8f901d42c3f60af834df625455ea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83776
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/common/block/psp/psp_smi_flash.c
1 file changed, 43 insertions(+), 3 deletions(-)
Approvals:
Martin Roth: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c
index 367baef..420fb94 100644
--- a/src/soc/amd/common/block/psp/psp_smi_flash.c
+++ b/src/soc/amd/common/block/psp/psp_smi_flash.c
@@ -72,6 +72,19 @@
return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id));
}
+static u64 get_psp_spi_info_id(struct mbox_pspv2_cmd_spi_info *cmd_buf)
+{
+ return read64(&cmd_buf->req.target_nv_id);
+}
+
+static void set_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf,
+ u64 lba, u64 block_size, u64 num_blocks)
+{
+ write64(&cmd_buf->req.lba, lba);
+ write64(&cmd_buf->req.block_size, block_size);
+ write64(&cmd_buf->req.num_blocks, num_blocks);
+}
+
static const char *id_to_region_name(u64 target_nv_id)
{
switch (target_nv_id) {
@@ -117,7 +130,7 @@
return rdev_chain(rstore, rdev, 0, region_device_sz(rdev));
}
-static inline enum mbox_p2c_status find_psp_spi_flash_device_region(u64 target_nv_id,
+static enum mbox_p2c_status find_psp_spi_flash_device_region(u64 target_nv_id,
struct region_device *store,
const struct spi_flash **flash)
{
@@ -135,7 +148,7 @@
return MBOX_PSP_SUCCESS;
}
-static inline bool spi_controller_available(void)
+static bool spi_controller_available(void)
{
return !(spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED);
}
@@ -144,13 +157,40 @@
{
struct mbox_pspv2_cmd_spi_info *const cmd_buf =
(struct mbox_pspv2_cmd_spi_info *)buffer;
+ const struct spi_flash *flash;
+ struct region_device store;
+ u64 target_nv_id;
+ u64 block_size;
+ u64 num_blocks;
+ enum mbox_p2c_status ret;
printk(BIOS_SPEW, "PSP: SPI info request\n");
if (!is_valid_psp_spi_info(cmd_buf))
return MBOX_PSP_COMMAND_PROCESS_ERROR;
- return MBOX_PSP_UNSUPPORTED;
+ if (!spi_controller_available()) {
+ printk(BIOS_NOTICE, "PSP: SPI controller busy\n");
+ return MBOX_PSP_SPI_BUSY;
+ }
+
+ target_nv_id = get_psp_spi_info_id(cmd_buf);
+
+ ret = find_psp_spi_flash_device_region(target_nv_id, &store, &flash);
+
+ if (ret != MBOX_PSP_SUCCESS)
+ return ret;
+
+ block_size = flash->sector_size;
+
+ if (!block_size)
+ return MBOX_PSP_COMMAND_PROCESS_ERROR;
+
+ num_blocks = region_device_sz(&store) / block_size;
+
+ set_psp_spi_info(cmd_buf, 0, block_size, num_blocks);
+
+ return MBOX_PSP_SUCCESS;
}
enum mbox_p2c_status psp_smi_spi_read(struct mbox_default_buffer *buffer)
--
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Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I19041a27a9e8f901d42c3f60af834df625455ea6
Gerrit-Change-Number: 83776
Gerrit-PatchSet: 4
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com>
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83775?usp=email )
Change subject: soc/amd/common/psp_smi_flash: add spi_controller_available
......................................................................
soc/amd/common/psp_smi_flash: add spi_controller_available
The SPI_SEMAPHORE_DRIVER_LOCKED bit in the SPI_MISC_CNTRL register
doesn't affect the hardware, but it re-used by AMD as a semaphore to
synchronize the access to the SPI controller between SMM and non-SMM
software like an OS-level driver. Since it doesn't affect the hardware,
it's marked as reserved in the PPRs. Add the 'spi_controller_available'
helper function to check this bit to see if some software or driver
outside of SMM is currently using the SPI flash controller to avoid
interfering with that operation.
This patch is a slightly reworked version of parts of CB:65523.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
Change-Id: I49218e03a5dd555b2b2d34eaad86673e9fc908c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83775
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/common/block/include/amdblocks/spi.h
M src/soc/amd/common/block/psp/psp_smi_flash.c
2 files changed, 9 insertions(+), 0 deletions(-)
Approvals:
Martin Roth: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index babe635..eafc2c2 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -77,6 +77,9 @@
#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1)
#define SPI_MISC_CNTRL 0xfc
+/* AMD has re-purposed this unused SPI controller register bit as a semaphore to synchronize
+ access to the SPI controller between SMM and non-SMM software/OS driver. */
+#define SPI_SEMAPHORE_DRIVER_LOCKED BIT(4)
struct spi_config {
/*
diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c
index 4c83fcd..367baef 100644
--- a/src/soc/amd/common/block/psp/psp_smi_flash.c
+++ b/src/soc/amd/common/block/psp/psp_smi_flash.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/spi.h>
#include <boot_device.h>
#include <commonlib/region.h>
#include <console/console.h>
@@ -134,6 +135,11 @@
return MBOX_PSP_SUCCESS;
}
+static inline bool spi_controller_available(void)
+{
+ return !(spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED);
+}
+
enum mbox_p2c_status psp_smi_spi_get_info(struct mbox_default_buffer *buffer)
{
struct mbox_pspv2_cmd_spi_info *const cmd_buf =
--
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Gerrit-Branch: main
Gerrit-Change-Id: I49218e03a5dd555b2b2d34eaad86673e9fc908c3
Gerrit-Change-Number: 83775
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com>
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83774?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/amd/common/psp_smi_flash: add find_psp_spi_flash_device_region
......................................................................
soc/amd/common/psp_smi_flash: add find_psp_spi_flash_device_region
Add 'find_psp_spi_flash_device_region' to get a pointer to the spi_flash
struct of the SPI flash used in the system and the region_device struct
for the target FMAP region specified by the target NV ID from the PSP
to x86 mailbox command. In order to have small patches, the newly added
static 'find_psp_spi_flash_device_region' function is marked as inline;
that inline will be removed in a following patch that calls this new
function.
This patch is a slightly reworked version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
Change-Id: I64b8fba2392de46ecd4c786cef0d5b6acdbd865a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83774
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/common/block/psp/psp_smi_flash.c
1 file changed, 67 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c
index f1b9d85..4c83fcd 100644
--- a/src/soc/amd/common/block/psp/psp_smi_flash.c
+++ b/src/soc/amd/common/block/psp/psp_smi_flash.c
@@ -1,7 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <boot_device.h>
+#include <commonlib/region.h>
#include <console/console.h>
#include <device/mmio.h>
+#include <fmap.h>
+#include <spi_flash.h>
#include <types.h>
#include "psp_def.h"
@@ -67,6 +71,69 @@
return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id));
}
+static const char *id_to_region_name(u64 target_nv_id)
+{
+ switch (target_nv_id) {
+ case SMI_TARGET_NVRAM:
+ return "PSP_NVRAM";
+ case SMI_TARGET_RPMC_NVRAM:
+ return "PSP_RPMC_NVRAM";
+ }
+ return NULL;
+}
+
+/*
+ * Do not cache the location to cope with flash changing underneath (e.g. due
+ * to an update)
+ */
+static int lookup_store(u64 target_nv_id, struct region_device *rstore)
+{
+ /* read_rdev, write_rdev and store_irdev need to be static to not go out of scope when
+ this function returns */
+ static struct region_device read_rdev, write_rdev;
+ static struct incoherent_rdev store_irdev;
+ const char *name;
+ struct region region;
+ const struct region_device *rdev;
+
+ name = id_to_region_name(target_nv_id);
+ if (!name)
+ return -1;
+
+ if (fmap_locate_area(name, ®ion) < 0)
+ return -1;
+
+ if (boot_device_ro_subregion(®ion, &read_rdev) < 0)
+ return -1;
+
+ if (boot_device_rw_subregion(®ion, &write_rdev) < 0)
+ return -1;
+
+ rdev = incoherent_rdev_init(&store_irdev, ®ion, &read_rdev, &write_rdev);
+ if (rdev == NULL)
+ return -1;
+
+ return rdev_chain(rstore, rdev, 0, region_device_sz(rdev));
+}
+
+static inline enum mbox_p2c_status find_psp_spi_flash_device_region(u64 target_nv_id,
+ struct region_device *store,
+ const struct spi_flash **flash)
+{
+ *flash = boot_device_spi_flash();
+ if (*flash == NULL) {
+ printk(BIOS_ERR, "PSP: Unable to find SPI device\n");
+ return MBOX_PSP_COMMAND_PROCESS_ERROR;
+ }
+
+ if (lookup_store(target_nv_id, store) < 0) {
+ printk(BIOS_ERR, "PSP: Unable to find PSP SPI region\n");
+ return MBOX_PSP_COMMAND_PROCESS_ERROR;
+ }
+
+ return MBOX_PSP_SUCCESS;
+}
+
enum mbox_p2c_status psp_smi_spi_get_info(struct mbox_default_buffer *buffer)
{
struct mbox_pspv2_cmd_spi_info *const cmd_buf =
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I64b8fba2392de46ecd4c786cef0d5b6acdbd865a
Gerrit-Change-Number: 83774
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com>