Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk.
Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83814?usp=email
to look at the new patch set (#2).
Change subject: soc/amd/*: pass PSP NVRAM base and size to amdfwtool
......................................................................
soc/amd/*: pass PSP NVRAM base and size to amdfwtool
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa
which doesn't use/support this. This was previously only implemented for
Picasso, but not for the SoCs that support this, so add the support to
those other SoCs as well.
If a mainboard has an section named 'PSP_NVRAM' in its FMAP file, the
start and length of it in the flash will be passed to amdfwtool which
then adds the base and length to the corresponding type 0x04 PSP
directory table entry.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I785ede8eb0df2473a4390b2c305add20f38d7ede
---
M src/soc/amd/cezanne/Makefile.mk
M src/soc/amd/glinda/Makefile.mk
M src/soc/amd/mendocino/Makefile.mk
M src/soc/amd/phoenix/Makefile.mk
M src/soc/amd/stoneyridge/Makefile.mk
5 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/83814/2
--
To view, visit https://review.coreboot.org/c/coreboot/+/83814?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I785ede8eb0df2473a4390b2c305add20f38d7ede
Gerrit-Change-Number: 83814
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Attention is currently required from: Nicholas Chin, Pablo, Paul Menzel.
Hello Nicholas Chin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83817?usp=email
to look at the new patch set (#5).
Change subject: Fix space that broke a link on documentation rendering
......................................................................
Fix space that broke a link on documentation rendering
Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
Signed-off-by: Pablo Iranzo Gómez <Pablo.Iranzo(a)gmail.com>
---
M Documentation/getting_started/faq.md
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/83817/5
--
To view, visit https://review.coreboot.org/c/coreboot/+/83817?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
Gerrit-Change-Number: 83817
Gerrit-PatchSet: 5
Gerrit-Owner: Pablo <Pablo(a)Iranzo.io>
Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Pablo <Pablo(a)Iranzo.io>
Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>
Attention is currently required from: Jakub Czapiga, Yu-Ping Wu.
Julius Werner has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83765?usp=email )
Change subject: lib/string: Add strncat() and strcat() functions
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS3:
> I'll leave it for now because of the license issue (don't have time to re-write the inefficient libp […]
Right, but since you're writing these functions from scratch anyway, you could just upload them as BSD code right now. If you upload them like this they'll be GPL and that would make it complicated again to potentially merge things later.
Maybe at least start something in commonlib with these two functions (doesn't mean you have to port everything else right away too)?
File src/lib/string.c:
https://review.coreboot.org/c/coreboot/+/83765/comment/32bbdd4a_30fbed06?us… :
PS4, Line 119: strcpy(dst + strlen(dst), src);
Same applies here, obviously (same code as above just without the `count--` check).
--
To view, visit https://review.coreboot.org/c/coreboot/+/83765?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: If02fce0eafb4f6fa01d8bab17d87a32360f4ac83
Gerrit-Change-Number: 83765
Gerrit-PatchSet: 4
Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Julius Werner <jwerner(a)chromium.org>
Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com>
Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Comment-Date: Wed, 07 Aug 2024 18:23:43 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>
Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>
Attention is currently required from: Jakub Czapiga, Martin L Roth, Nico Huber.
Hello Jakub Czapiga, Martin L Roth, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83459?usp=email
to look at the new patch set (#12).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: tree: Add kconfig option for testing C23 dialect
......................................................................
tree: Add kconfig option for testing C23 dialect
This adds C23 dialect for testing and prepare for C23 dialect support.
Change-Id: I07db866bebfd25f1a60d18a3228ada2957500234
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M Makefile.mk
M src/Kconfig
M src/include/stdbool.h
M src/include/stddef.h
4 files changed, 25 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/83459/12
--
To view, visit https://review.coreboot.org/c/coreboot/+/83459?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I07db866bebfd25f1a60d18a3228ada2957500234
Gerrit-Change-Number: 83459
Gerrit-PatchSet: 12
Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>
Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Nico Huber <nico.h(a)gmx.de>
Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com>
Attention is currently required from: Nicholas Chin, Paul Menzel.
Pablo has posted comments on this change by Pablo. ( https://review.coreboot.org/c/coreboot/+/83817?usp=email )
Change subject: Fix space that broke a link on documentation rendering
......................................................................
Patch Set 3:
(1 comment)
File Documentation/getting_started/faq.md:
https://review.coreboot.org/c/coreboot/+/83817/comment/0ee93dee_82fe6f71?us… :
PS2, Line 87: (https://doc.coreboot.org/payloads.html)
> Add this on the new line?
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/83817?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
Gerrit-Change-Number: 83817
Gerrit-PatchSet: 3
Gerrit-Owner: Pablo <Pablo(a)Iranzo.io>
Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>
Gerrit-Comment-Date: Wed, 07 Aug 2024 18:08:57 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>
Attention is currently required from: Nicholas Chin, Pablo.
Hello Nicholas Chin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83817?usp=email
to look at the new patch set (#4).
Change subject: Fix space that broke a link on documentation rendering
......................................................................
Fix space that broke a link on documentation rendering
Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
---
M Documentation/getting_started/faq.md
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/83817/4
--
To view, visit https://review.coreboot.org/c/coreboot/+/83817?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
Gerrit-Change-Number: 83817
Gerrit-PatchSet: 4
Gerrit-Owner: Pablo <Pablo(a)Iranzo.io>
Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Pablo <Pablo(a)Iranzo.io>
Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>
Pablo has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/83817?usp=email )
Change subject: Fix space that broke a link on documentation rendering
......................................................................
Fix space that broke a link on documentation rendering
Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
---
M Documentation/getting_started/faq.md
1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/83817/3
--
To view, visit https://review.coreboot.org/c/coreboot/+/83817?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
Gerrit-Change-Number: 83817
Gerrit-PatchSet: 3
Gerrit-Owner: Pablo <Pablo(a)Iranzo.io>
Pablo has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83817?usp=email )
Change subject: Fix space that breaked link on documentation rendering
......................................................................
Fix space that breaked link on documentation rendering
Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
---
M Documentation/getting_started/faq.md
1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/83817/2
--
To view, visit https://review.coreboot.org/c/coreboot/+/83817?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
Gerrit-Change-Number: 83817
Gerrit-PatchSet: 2
Gerrit-Owner: Pablo <Pablo(a)Iranzo.io>
Pablo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83817?usp=email )
Change subject: Fix space that breaked link on documentation rendering
......................................................................
Fix space that breaked link on documentation rendering
Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
---
M Documentation/getting_started/faq.md
1 file changed, 41 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/83817/1
diff --git a/Documentation/getting_started/faq.md b/Documentation/getting_started/faq.md
index a92c5ca..1ec17a6 100644
--- a/Documentation/getting_started/faq.md
+++ b/Documentation/getting_started/faq.md
@@ -2,7 +2,6 @@
## General coreboot questions
-
### What is coreboot?
coreboot is a free and open software project designed to initialize
@@ -11,7 +10,6 @@
absolutely needed, then pass control to other software (a payload, in
coreboot parlance) in order to boot the operating system securely.
-
### What is a coreboot payload?
coreboot itself does not deal with boot media such as hard-drives,
@@ -20,7 +18,6 @@
software which does do those things must be used. coreboot supports
a large number of diverse payloads; see below for more details.
-
### Is coreboot the same as UEFI?
No. coreboot and UEFI are both system firmware that handle the
@@ -30,7 +27,6 @@
and making it easier to find and fix bugs. The result is a higher
overall security.
-
### What's the difference between coreboot and UEFI?
UEFI is actually a firmware specification, not a specific software
@@ -46,12 +42,11 @@
The UEFI specification also defines and allows for many things that are
outside of coreboot’s scope, including (but not limited to):
-* Boot device selection
-* Updating the firmware
-* A CLI shell
-* Network communication
-* An integrated setup menu
-
+- Boot device selection
+- Updating the firmware
+- A CLI shell
+- Network communication
+- An integrated setup menu
### Can coreboot boot operating systems that require UEFI?
@@ -66,27 +61,24 @@
with EDK2 supplying the UEFI boot interface and runtime services to
the operating system.
-
### What non-UEFI payloads does coreboot support?
-* SeaBIOS, behaves like a classic BIOS, allowing you to boot operating
+- SeaBIOS, behaves like a classic BIOS, allowing you to boot operating
systems that rely on the legacy interrupts.
-* GRUB can be used as a coreboot payload, and is currently the most
+- GRUB can be used as a coreboot payload, and is currently the most
common approach to full disk encryption (FDE).
-* A Linux kernel and initramfs stored alongside coreboot in the boot
+- A Linux kernel and initramfs stored alongside coreboot in the boot
ROM can also be used as a payload. In this scenario coreboot
initializes hardware, loads Linux from boot ROM into RAM, and
executes it. The embedded Linux environment can look for a target OS
kernel to load from local storage or over a network and execute it
using kexec. This is sometimes called LinuxBoot.
-* U-boot, depthcharge, FILO, etc.
+- U-boot, depthcharge, FILO, etc.
-There’s [https://doc.coreboot.org/payloads.html](https://doc.coreboot.org/payloads.
-html) with a list, although it’s not complete.
-
+There’s [https://doc.coreboot.org/payloads.html](https://doc.coreboot.org/payloads.h… with a list, although it’s not complete.
### What does coreboot leave in memory after it's done initializing the hardware?
@@ -99,7 +91,6 @@
In addition to CBMEM, on X86 systems, coreboot will typically set up
SMM, which will remain resident after coreboot exits.
-
## Platforms
### What’s the best coreboot platform for a user?
@@ -120,13 +111,12 @@
The coreboot project mantains a list of companies selling machines
which use coreboot on the [website](https://coreboot.org/users.html).
-
### What’s the best platform for coreboot development?
Similar to the best platform for users, the best platform for
developers very much depends on what a developer is trying to do.
-* QEMU is generally the easiest platform for coreboot development, just
+- QEMU is generally the easiest platform for coreboot development, just
because it’s easy to run anywhere. However, it’s possible for things
to work properly in QEMU but fail miserably on actual hardware.
@@ -160,7 +150,6 @@
specifications](https://chromium.googlesource.com/chromiumos/third_party/hd…
for these cables.
-
### What platforms does coreboot support?
The most accurate way to determine what systems coreboot supports is by
@@ -172,7 +161,6 @@
([https://coreboot.org/status/board-status.html](https://coreboot.org/status/…),
however this does not currently show supported board variants.
-
## coreboot Development
### Can coreboot be ported to [this board]?
@@ -184,30 +172,31 @@
Intel Platforms:
-* coreboot only supports a few northbridges (back when northbridges
+- coreboot only supports a few northbridges (back when northbridges
were on a separate package), and there's next to no support for
"server" platforms (multi-socket and similar things). Here's a list
of more recent supported Intel processors:
- * Alder Lake (2021 - Core Gen 12)
- * Apollo Lake (2016 - Atom)
- * Baytrail (2014 - Atom)
- * Braswell (2016 - Atom)
- * Broadwell (2014 - Core Gen 5)
- * Comet Lake (2019 - Core Gen 10)
- * Cannon Lake (2018 - Core Gen 8/9)
- * Denverton (2017)
- * Elkhart lake (2021 - Atom)
- * Haswell (2013 - Core Gen 4)
- * Ivy Bridge (2012 - Core Gen 3)
- * Jasper Lake (2021 - Atom)
- * Kaby Lake (2016 - Core Gen 7/8)
- * Meteor Lake (2023 - Gen 1 Ultra-mobile)
- * Sandy Bridge (2011 - Core Gen 2)
- * Sky Lake (2015 - Core Gen 6)
- * Tiger Lake (2020 - Core Gen 11)
- * Whiskey Lake (2018 - Core Gen 8)
-* Intel Boot Guard is a security feature which tries to prevent loading
+ - Alder Lake (2021 - Core Gen 12)
+ - Apollo Lake (2016 - Atom)
+ - Baytrail (2014 - Atom)
+ - Braswell (2016 - Atom)
+ - Broadwell (2014 - Core Gen 5)
+ - Comet Lake (2019 - Core Gen 10)
+ - Cannon Lake (2018 - Core Gen 8/9)
+ - Denverton (2017)
+ - Elkhart lake (2021 - Atom)
+ - Haswell (2013 - Core Gen 4)
+ - Ivy Bridge (2012 - Core Gen 3)
+ - Jasper Lake (2021 - Atom)
+ - Kaby Lake (2016 - Core Gen 7/8)
+ - Meteor Lake (2023 - Gen 1 Ultra-mobile)
+ - Sandy Bridge (2011 - Core Gen 2)
+ - Sky Lake (2015 - Core Gen 6)
+ - Tiger Lake (2020 - Core Gen 11)
+ - Whiskey Lake (2018 - Core Gen 8)
+
+- Intel Boot Guard is a security feature which tries to prevent loading
unauthorized firmware by the mainboard. If supported by the platform,
and the platform is supported by intelmetool, you should check if Boot
Guard is enabled. If it is, then getting coreboot to run will be
@@ -218,34 +207,33 @@
AMD Ryzen-based platforms:
-* The AMD platforms Ryzen-based platforms unfortunately are currently
+- The AMD platforms Ryzen-based platforms unfortunately are currently
not well supported outside of the Chromebooks (and AMD reference
boards) currently in the tree.
The responsible teams are trying to fix this, but currently it's
**very** difficult to do a new port. Recent supported SoCs:
- * Stoney Ridge
- * Picasso
- * Cezanne
- * Mendocino
- * Phoenix
+ - Stoney Ridge
+ - Picasso
+ - Cezanne
+ - Mendocino
+ - Phoenix
General notes:
-* Check the output of `lspci` to determine what processor/chipset
+- Check the output of `lspci` to determine what processor/chipset
family your system has. Processor/chipset support is the most
important to determine if a board can be ported.
-* Check the output of `superiotool` to see if it detects the Super I/O
+- Check the output of `superiotool` to see if it detects the Super I/O
on the system. You can also check board schematics and/or boardviews
if you can find them, or physically look at the mainboard for a chip
from one of the common superio vendors.
-* Check what EC your system has (mostly applicable to laptops, but some
+- Check what EC your system has (mostly applicable to laptops, but some
desktops have EC-like chips). You will likely need to refer to the
actual board or schematics/boardviews for this. Physical observation
is the most accurate identification procedure; software detection can
then be used to double-check if the chip is correct, but one should
not rely on software detection alone to identify an EC.
-
### How do I port coreboot to [this board]?
A critical piece for anyone attempting to do a board port is to make
@@ -259,7 +247,6 @@
one of the [various community
forums](https://doc.coreboot.org/community/forums.html).
-
### What about the Intel ME?
There seems to be a lot of FUD about what the ME can and can’t do.
@@ -273,7 +260,6 @@
not necessary to run coreboot to modify the ME, and running coreboot
does not imply anything about the ME's operational state.
-
#### A word of caution about the modifying ME
Messing with the ME firmware can cause issues, and this is outside the
--
To view, visit https://review.coreboot.org/c/coreboot/+/83817?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
Gerrit-Change-Number: 83817
Gerrit-PatchSet: 1
Gerrit-Owner: Pablo <Pablo(a)Iranzo.io>