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Change subject: soc/amd/*: pass PSP RPMC NVRAM base and size to amdfwtool
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/cmn/pmc: Add API to dump silicon QDF information
......................................................................
Patch Set 10:
(11 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83784/comment/208143cd_ae801d1c?us… :
PS6, Line 7: soc/intel/common:
> soc/intel/cmn/pmc
Done. Updated to patchset#10
https://review.coreboot.org/c/coreboot/+/83784/comment/e051d281_b5d4fc06?us… :
PS6, Line 7: Add SoC QDF read function
> ``` […]
Thanks for the suggestion. Updated by patchset#10
https://review.coreboot.org/c/coreboot/+/83784/comment/c6171dfa_099cb626?us… :
PS6, Line 13:
> what we shall do with this QDF information hasn't been mentioned in this CL. […]
thanks for comments. I added more information to the commit message by patchset#10, please let me know if more information is needed.
File src/soc/intel/common/block/include/intelblocks/pmc_ipc.h:
https://review.coreboot.org/c/coreboot/+/83784/comment/6d4f8a39_42df68cb?us… :
PS6, Line 45: /* IPC command for accessing SoC registers */
: #define PMC_IPC_CMD_SOC_REG_ACC 0xAA
: #define PMC_IPC_CMD_SUBCMD_SOC_REG_RD 0x00
: #if CONFIG(SOC_QDF_DYNAMIC_READ_PMC)
: #define PMC_IPC_CMD_REGID_SOC_QDF 0x03
: #endif /* SOC_QDF_DYNAMIC_READ_PMC */
> please don't use any CPP to guard the macro. […]
Sure, done by patchset#10
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/83784/comment/035e1ade_761e631f?us… :
PS6, Line 271: #if CONFIG(SOC_QDF_DYNAMIC_READ_PMC)
> u don't need this guard
Done. Updated by patchset#10
File src/soc/intel/common/block/pmc/Kconfig:
https://review.coreboot.org/c/coreboot/+/83784/comment/e8a2346f_2951d31e?us… :
PS6, Line 89: depends on SOC_INTEL_COMMON_BLOCK_PMC
: depends on PMC_IPC_ACPI_INTERFACE
> ```suggestion […]
Done. Updated by patchset#10
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/83784/comment/3f82d62d_52aef8e7?us… :
PS6, Line 888: This function reads SoC QDF information using PMC interface.
> ```suggestion […]
Thanks for the suggestion. I updated the comments after removing the return type. Please let me know if you have further suggestion on this.
https://review.coreboot.org/c/coreboot/+/83784/comment/d4fcfb74_01097358?us… :
PS6, Line 891: int pmc_read_qdf(void)
> looks like we are not returning anything, rather we are just dumping? […]
I removed the return value of the function and renamed the function name to pmc_dump_soc_qdf_info. Thanks.
https://review.coreboot.org/c/coreboot/+/83784/comment/c483d2b9_c2e3f821?us… :
PS6, Line 891: int pmc_read_qdf(void)
: {
> ```suggestion […]
Thanks. Updated by patchset#10
https://review.coreboot.org/c/coreboot/+/83784/comment/d2743adf_4ea7e0cd?us… :
PS6, Line 908: 0
> error as in `-1`
Thanks. I removed the return value of the function by patchset#10.
https://review.coreboot.org/c/coreboot/+/83784/comment/f6c0f372_21fd7202?us… :
PS6, Line 918: } else {
: printk(BIOS_INFO, "SoC QDF not available\n");
: }
> do we really care about this print?
I removed it by patchset#10.
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Hello Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jérémy Compostella, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/cmn/pmc: Add API to dump silicon QDF information
......................................................................
soc/intel/cmn/pmc: Add API to dump silicon QDF information
This adds pmc_dump_soc_qdf_info function and PMC_IPC_CMD_SOC_REG_ACC
PMC IPC Command to read and print Intel SoC QDF information using PMC
interface if SOC_QDF_DYNAMIC_READ_PMC is enabled. QDF read command is
supported from Panther Lake SoC.
QDF is a four digit code that can be used to identify enabled features
and capabilities. This information will be useful to debug issues
found during the development phase and in the field as well.
Change-Id: I927da1a97e6dad4ee54c4d2256fea5813a0ce43d
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/Kconfig
M src/soc/intel/common/block/pmc/pmclib.c
4 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/83784/10
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Change subject: [UNTESTED] Makefile: Move `--no-warn-rwx-segments' into xcompile
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
Fixes issue caused by CB:83559 for me
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Change subject: Makefile.mk: Remove linker warning on RWX segments
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> `xcompile` kind of abstracts the toolchain version. It has code for exactly […]
fixes the issue for me
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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
18 files changed, 1,362 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/61
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Sergii Dmytruk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/67057?usp=email )
Change subject: drivers/ipmi: add Block Transfer (BT) interface
......................................................................
Patch Set 34:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67057/comment/483cca6c_62778661?us… :
PS33, Line 14:
> How did you test this? Can it be tested with QEMU? Maybe mention the datasheet name?
Updated the comment. QEMU does support some BMCs and looks like it should be possible to enable one along with the main CPU ([pdf](https://www.linux-kvm.org/images/7/76/03x08-Juniper-Corey_Minyard-Usin…) but I tested the implementation on Talos II system where a watchdog needed to be set and KCS isn't supported.
File Documentation/drivers/index.md:
https://review.coreboot.org/c/coreboot/+/67057/comment/5f750540_37da21e0?us… :
PS33, Line 15: BT
> Include Block Transfer?
Added in parenthesis.
File Documentation/drivers/ipmi_bt.md:
https://review.coreboot.org/c/coreboot/+/67057/comment/acc4c60b_fead1184?us… :
PS33, Line 14: ```
: chip drivers/ipmi
: device pnp e4.0 on end # IPMI BT
: end
: ```
> I’d prefer intending by four spaces. But feel free to mark as resolved.
Edited. It was formatting that I preserved from KCS documentation.
https://review.coreboot.org/c/coreboot/+/67057/comment/a1a58e52_d839891e?us… :
PS33, Line 22: The following registers can be set:
> Where can they be set?
In a device tree. Updated.
File src/drivers/ipmi/Kconfig:
https://review.coreboot.org/c/coreboot/+/67057/comment/6e0eb4e7_ccd0a608?us… :
PS33, Line 85: for implementation
> *an* implementation? […]
Done
File src/drivers/ipmi/ipmi_bt_ops.c:
https://review.coreboot.org/c/coreboot/+/67057/comment/130d93a0_efcac008?us… :
PS33, Line 103: printk(BIOS_ERR, "%s: Unsupported device type\n",
> Print both values?
Done
https://review.coreboot.org/c/coreboot/+/67057/comment/9d358a99_82443e7a?us… :
PS33, Line 106: printk(BIOS_ERR, "%s: Base address needs to be aligned to 4\n",
> Print the address?
Done
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Hello Christian Walter, Felix Held, Jonathan Zhang, Krystian Hebel, Martin L Roth, Martin Roth, Michał Żygowski, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/ipmi: add Block Transfer (BT) interface
......................................................................
drivers/ipmi: add Block Transfer (BT) interface
Unlike already implemented Keyboard Controller Style (KCS) interface
Block Transfer interface is not byte-oriented and implies that device is
capable of buffering a command before processing it. Another difference
is that polling can be replaced with interrupts, though this isn't used
by this implementation.
More details can be found in "Intelligent Platform Management Interface
Specification", v2.0, Rev. 1.1
This was tested on Talos II (OpenPower platform) by Raptor Computing
Systems.
Change-Id: Idb67972d1c38bbae04c7b4de3405350c229a05b9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M Documentation/drivers/index.md
A Documentation/drivers/ipmi_bt.md
M src/drivers/ipmi/Kconfig
M src/drivers/ipmi/Makefile.mk
A src/drivers/ipmi/ipmi_bt.c
A src/drivers/ipmi/ipmi_bt.h
A src/drivers/ipmi/ipmi_bt_ops.c
M src/drivers/ipmi/ipmi_ops_premem.c
8 files changed, 409 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/67057/34
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Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
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Patch Set 23:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83705/comment/cea71d2e_e32011b1?us… :
PS20, Line 12: BUG=NA
> i guess there is a bug (b/352651132) which should be enough to give answer to the https://review. […]
Acknowledged
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Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
......................................................................
Patch Set 23:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83705/comment/f1f82bcc_0518144a?us… :
PS20, Line 15: Cq-Depend: CB:83769, CB:83770
> This is a thing specific to the ChromeOS CI, it does not work here. […]
Understood, removed. Thanks
https://review.coreboot.org/c/coreboot/+/83705/comment/3df067d6_7f949e90?us… :
PS20, Line 15: Cq-Depend: CB:83769, CB:83770
> please remove this. […]
Removed, thanks.
File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/83705/comment/21546af8_9d427522?us… :
PS20, Line 105: config CHROMEOS_ENABLE_ESOL
> Does this Kconfig actually do anything? I don't see it referenced anywhere? […]
As Subrata mentioned, b/352651132 provides some context for the change. Added the bug in the commit message as well.
Thanks
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