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Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 62:
(15 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/3d3c33c8_60c2df1d?us… :
PS36, Line 53: 22
> Yes, it should be 4+8+4=16 for H SKU.
Acknowledged
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/cc9355c5_b66c6d7b?us… :
PS48, Line 95: config P2SB_2_PCR_BASE_ADDRESS
> Can we use similar definition as PCR2_BASE_ADDRESS?
same comment for this. If Subrata agress, we can make the change.
File src/soc/intel/pantherlake/bootblock/pcd.c:
https://review.coreboot.org/c/coreboot/+/83354/comment/975361b7_d34e5f54?us… :
PS47, Line 27: #define PCR_PSFX_TO_SHDW_BAR0 0
> Remove unused definitions […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83354/comment/2d8dbf3a_bc967dba?us… :
PS47, Line 35: #define PCR_DMI_ACPIBA 0x27B4
> Remove unused definitions […]
Acknowledged
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/c79788f8_6b593246?us… :
PS61, Line 23: #define EP_BASE_ADDRESS 0xfeda1000
> Can you check if this is sill used for PTL?
Hi Will, sure i will check and update.
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/8861bbed_bf8ce229?us… :
PS48, Line 20: 2000000
> Can we use MiB instead of direct hex value? And Can we also update all size value by using KiB and […]
We can come back and make the changes in refactoring of bootblock. Currently this way writing is similar to being used with n-1 platforms.
https://review.coreboot.org/c/coreboot/+/83354/comment/3a1c5e7c_31dd7daf?us… :
PS48, Line 72: #define P2SB2_BAR CONFIG_P2SB_2_PCR_BASE_ADDRESS
> Can we use like PCR2_BASE_ADDRESS?
This name was suggested by Subrata, we had resolved this query earlier to be using "P2SB_2_PCR_BASE_ADDRESS". Let me know what suites, will update accordingly.
File src/soc/intel/pantherlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/812d61c2_a2127197?us… :
PS61, Line 75: #define PCI_DEV_TCSS_XDCI _PCI_DEV(TCSS, 1)
> Would you move this to the line between 78-79, after PCI_DEV_TCSS_XHCI?
Acknowledged
https://review.coreboot.org/c/coreboot/+/83354/comment/435cde09_696ca38b?us… :
PS61, Line 97:
> remove the tab to align the indentation
Acknowledged
https://review.coreboot.org/c/coreboot/+/83354/comment/251b4911_090579d0?us… :
PS61, Line 111: #define PCI_DEV_IEH_0 _PCI_DEV(XHCI, 5)
: #define PCI_DEV_CNVI_BT _PCI_DEV(XHCI, 7)
> move this after line 116-PCI_DEV_CNVI_WIFI?
Acknowledged
File src/soc/intel/pantherlake/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/024ceb3c_047b3b2d?us… :
PS48, Line 14: #define PID_PSF15 0xB4
> For PID_PSFn, can you add only used define? […]
Yes, but as per Subrata, we have to push all the avaliable PIDs.
https://review.coreboot.org/c/coreboot/+/83354/comment/d1583c05_3f0a5cad?us… :
PS48, Line 26: #define PID_DMI 0x2F
> This is dummy value. Can you check if we remove this cause build error? […]
Sure, i will update this with my build recipe on fatcat MB.
https://review.coreboot.org/c/coreboot/+/83354/comment/57977e05_e6457e18?us… :
PS48, Line 27: #define PID_NPK 0x8C
> PID_NPK is used?
Not used, removed.
https://review.coreboot.org/c/coreboot/+/83354/comment/f1c49962_81dfacb7?us… :
PS48, Line 28: #define PID_XHCI 0x3A
> Is this value is correct? according to BIOS reference code USB Host controller P2SB id is 0x09.
Acknowledged
File src/soc/intel/pantherlake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/237711d8_adc441f0?us… :
PS61, Line 80:
> suggesting to use tabs instead of spaces between GPE_STS_RSVD and GPE_STD
Acknowledged
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Attention is currently required from: Cliff Huang, Jérémy Compostella, Ravishankar Sarawadi, Subrata Banik.
Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83635?usp=email
to look at the new patch set (#62).
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
18 files changed, 1,362 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/62
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,276 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/62
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Wonkyu Kim has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 61:
(10 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/a18eb875_4ccf6d26?us… :
PS36, Line 53: 22
> I guess we need to revisit this. […]
Yes, it should be 4+8+4=16 for H SKU.
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/491f98e0_0eb8ff0c?us… :
PS48, Line 95: config P2SB_2_PCR_BASE_ADDRESS
Can we use similar definition as PCR2_BASE_ADDRESS?
File src/soc/intel/pantherlake/bootblock/pcd.c:
https://review.coreboot.org/c/coreboot/+/83354/comment/25b7a702_ebdd6947?us… :
PS47, Line 27: #define PCR_PSFX_TO_SHDW_BAR0 0
Remove unused definitions
#define PCR_PSFX_TO_SHDW_BAR0 0
#define PCR_PSFX_TO_SHDW_BAR1 0x4
#define PCR_PSFX_TO_SHDW_BAR2 0x8
#define PCR_PSFX_TO_SHDW_BAR3 0xC
https://review.coreboot.org/c/coreboot/+/83354/comment/eaf4a644_6b79b694?us… :
PS47, Line 35: #define PCR_DMI_ACPIBA 0x27B4
Remove unused definitions
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/387fed74_02bd2023?us… :
PS48, Line 20: 2000000
Can we use MiB instead of direct hex value? And Can we also update all size value by using KiB and MiB for readablity?
https://review.coreboot.org/c/coreboot/+/83354/comment/a970f517_3e25f3da?us… :
PS48, Line 72: #define P2SB2_BAR CONFIG_P2SB_2_PCR_BASE_ADDRESS
Can we use like PCR2_BASE_ADDRESS?
File src/soc/intel/pantherlake/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/fac8af6a_5e6aa795?us… :
PS48, Line 14: #define PID_PSF15 0xB4
For PID_PSFn, can you add only used define?
It looks only PID_PSF8 is used for Pantherlalke.
https://review.coreboot.org/c/coreboot/+/83354/comment/ecc8983f_55b33ad4?us… :
PS48, Line 26: #define PID_DMI 0x2F
This is dummy value. Can you check if we remove this cause build error?
If this cause build error, can you add comments this is dummy value which we don't use?
https://review.coreboot.org/c/coreboot/+/83354/comment/dbbf9bf5_0ae5aba4?us… :
PS48, Line 27: #define PID_NPK 0x8C
PID_NPK is used?
https://review.coreboot.org/c/coreboot/+/83354/comment/abc8e530_7b95bdfc?us… :
PS48, Line 28: #define PID_XHCI 0x3A
Is this value is correct? according to BIOS reference code USB Host controller P2SB id is 0x09.
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Attention is currently required from: Bao Zheng, Jason Nien, Jon Murphy, Martin Roth, Matt DeVillier, Paul Menzel, Zheng Bao.
Hello Jason Nien, Martin Roth, Matt DeVillier, Zheng Bao, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83646?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/skyrim: Combine the function port_descriptors for variants
......................................................................
mb/google/skyrim: Combine the function port_descriptors for variants
Remove the weak function. Combine all the getting descriptors together.
BUG=b:279144932
TEST=Build
Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/port_descriptors.h
M src/mainboard/google/skyrim/variants/baseboard/port_descriptors.c
M src/mainboard/google/skyrim/variants/markarth/Makefile.mk
D src/mainboard/google/skyrim/variants/markarth/port_descriptors.c
M src/mainboard/google/skyrim/variants/winterhold/Makefile.mk
D src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c
6 files changed, 45 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83646/6
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Attention is currently required from: Jakub Czapiga, Julius Werner.
Yu-Ping Wu has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83765?usp=email )
Change subject: lib/string: Add strncat() and strcat() functions
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS3:
> Maybe at least start something in commonlib with these two functions (doesn't mean you have to port everything else right away too)?
Sure. I can do that.
File src/lib/string.c:
https://review.coreboot.org/c/coreboot/+/83765/comment/71e68dfd_abde9edd?us… :
PS4, Line 119: strcpy(dst + strlen(dst), src);
> Same applies here, obviously (same code as above just without the `count--` check).
I still don't understand the problem of the current implementation. If I write
```
char *ptr = dst + strlen(dst);
while (*src)
*ptr++ = *src++;
*ptr = '\0';
```
isn't that exactly equivalent to calling `strcpy()`?
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