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Change subject: soc/mediatek/common: Refactor EINT driver
......................................................................
Patch Set 3:
(2 comments)
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/83703/comment/0c83849b_cf675842?us… :
PS2, Line 122: void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit);
: void *eint_find_reg_addr(gpio_t gpio);
> Since these functions are still declared here in gpio_common.h and are related to gpio, how about: […]
Done
https://review.coreboot.org/c/coreboot/+/83703/comment/ed495bca_0c73c6ba?us… :
PS2, Line 123: void
> struct eint_regs
Done
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Change subject: soc/mediatek/common: Refactor EINT driver
......................................................................
soc/mediatek/common: Refactor EINT driver
Refactor EINT driver by
- Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to
`gpio_calc_eint_pos_bit`.
- Implment `gpio_get_eint_reg` to obtain EINT base address.
This change is prepared for the driver change in MT8196.
BUG=b:334723688
TEST=EINT works on Geralt
Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
M src/soc/mediatek/common/gpio.c
A src/soc/mediatek/common/gpio_eint_v1.c
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/mt8183/Makefile.mk
M src/soc/mediatek/mt8186/Makefile.mk
M src/soc/mediatek/mt8188/Makefile.mk
M src/soc/mediatek/mt8192/Makefile.mk
M src/soc/mediatek/mt8195/Makefile.mk
8 files changed, 37 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/83703/3
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Change subject: soc/intel/common/block/gpmr: Allow soc to have specific gpmr definition
......................................................................
Patch Set 10: Code-Review+2
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpmr.h:
https://review.coreboot.org/c/coreboot/+/83317/comment/21e1b710_cea4fe2a?us… :
PS3, Line 10: #include <soc/gpmr.h>
> To remove the word 'PCR' in the config item might make sense (e.g. […]
Done
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Change subject: soc/intel/mtl: enable FSP uGOP config in MTL for eSOL
......................................................................
Patch Set 18:
(1 comment)
File src/soc/intel/meteorlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83769/comment/de71406d_3215f6a0?us… :
PS18, Line 514: FSP_UGOP_EARLY_SIGN_OF_LIFE
> That wouldn't be correct, though: if using libgfxinit for eSOL, the FSP-M UPDs don't need to be populated.
eSOL is a feature that can be implemented using two different technologies:
(A) FSP uGOP
(B) libgfxinit
For (A), we need to override UPD, which is where this file comes in.
For MTL onwards on the Intel platform, libgfxinit support is not POR. So, the only option we have now is supporting eSOL using uGOP. Therefore, whether we are using FSP_UGOP_EARLY_SIGN_OF_LIFE or CHROMEOS_ENABLE_ESOL, both are eventually the same starting with the MTL platform.
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Change subject: soc/intel/common/block/gpio/gpio.c: Improve GPIO debug infos
......................................................................
Patch Set 10: Code-Review+2
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Change subject: soc/intel/common/block/gpmr: Allow soc to have specific gpmr definition
......................................................................
soc/intel/common/block/gpmr: Allow soc to have specific gpmr definition
This patch add a new Kconfig HAVE_SPECIFIC_GPMR and use it to include
soc/gpmr.h if necessary.
Change-Id: I94797a72af75fc96ab2cacb1d46b581605a15387
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/soc/intel/common/block/gpmr/Kconfig
M src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h
2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/83317/10
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Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
......................................................................
soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/soc/intel/snowridge/Kconfig
A src/soc/intel/snowridge/Makefile.mk
A src/soc/intel/snowridge/acpi.c
A src/soc/intel/snowridge/acpi/hostbridges.asl
A src/soc/intel/snowridge/acpi/ith.asl
A src/soc/intel/snowridge/acpi/lpc.asl
A src/soc/intel/snowridge/acpi/pch_irqs.asl
A src/soc/intel/snowridge/acpi/pci_irqs.asl
A src/soc/intel/snowridge/acpi/pcie.asl
A src/soc/intel/snowridge/acpi/pcie_port.asl
A src/soc/intel/snowridge/acpi/pmc.asl
A src/soc/intel/snowridge/acpi/sata0.asl
A src/soc/intel/snowridge/acpi/sata2.asl
A src/soc/intel/snowridge/acpi/smbus.asl
A src/soc/intel/snowridge/acpi/southcluster.asl
A src/soc/intel/snowridge/acpi/uncore.asl
A src/soc/intel/snowridge/bootblock/bootblock.c
A src/soc/intel/snowridge/bootblock/bootblock.h
A src/soc/intel/snowridge/bootblock/early_uart_init.c
A src/soc/intel/snowridge/chip.c
A src/soc/intel/snowridge/chip.h
A src/soc/intel/snowridge/common/fsp_hob.c
A src/soc/intel/snowridge/common/fsp_hob.h
A src/soc/intel/snowridge/common/gpio.c
A src/soc/intel/snowridge/common/hob_display.c
A src/soc/intel/snowridge/common/kti_cache.c
A src/soc/intel/snowridge/common/kti_cache.h
A src/soc/intel/snowridge/common/pmclib.c
A src/soc/intel/snowridge/common/reset.c
A src/soc/intel/snowridge/common/spi.c
A src/soc/intel/snowridge/common/uart8250mem.c
A src/soc/intel/snowridge/common/uart8250mem.h
A src/soc/intel/snowridge/common/upd_display.c
A src/soc/intel/snowridge/cpu.c
A src/soc/intel/snowridge/finalize.c
A src/soc/intel/snowridge/heci.c
A src/soc/intel/snowridge/hob_iiouds.h
A src/soc/intel/snowridge/hqm.c
A src/soc/intel/snowridge/include/soc/acpi.h
A src/soc/intel/snowridge/include/soc/cpu.h
A src/soc/intel/snowridge/include/soc/gpio.h
A src/soc/intel/snowridge/include/soc/gpio_defs.h
A src/soc/intel/snowridge/include/soc/gpio_snr.h
A src/soc/intel/snowridge/include/soc/iomap.h
A src/soc/intel/snowridge/include/soc/irq.h
A src/soc/intel/snowridge/include/soc/itss.h
A src/soc/intel/snowridge/include/soc/lpc.h
A src/soc/intel/snowridge/include/soc/msr.h
A src/soc/intel/snowridge/include/soc/nvs.h
A src/soc/intel/snowridge/include/soc/p2sb.h
A src/soc/intel/snowridge/include/soc/pci_devs.h
A src/soc/intel/snowridge/include/soc/pci_ids.h
A src/soc/intel/snowridge/include/soc/pcr_gpmr.h
A src/soc/intel/snowridge/include/soc/pcr_ids.h
A src/soc/intel/snowridge/include/soc/pm.h
A src/soc/intel/snowridge/include/soc/pmc.h
A src/soc/intel/snowridge/include/soc/sata.h
A src/soc/intel/snowridge/include/soc/smbus.h
A src/soc/intel/snowridge/include/soc/soc_chip.h
A src/soc/intel/snowridge/include/soc/systemagent.h
A src/soc/intel/snowridge/lockdown.c
A src/soc/intel/snowridge/lpc.c
A src/soc/intel/snowridge/memmap.c
A src/soc/intel/snowridge/nis.c
A src/soc/intel/snowridge/qat.c
A src/soc/intel/snowridge/ramstage.h
A src/soc/intel/snowridge/romstage/gpio_snr.c
A src/soc/intel/snowridge/romstage/romstage.c
A src/soc/intel/snowridge/sata.c
A src/soc/intel/snowridge/smihandler.c
A src/soc/intel/snowridge/sriov.c
A src/soc/intel/snowridge/systemagent.c
72 files changed, 5,848 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/11
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Change subject: soc/intel/cmn/pmc: Add API to dump silicon QDF information
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
> Hi Subrata, this new API change is added for Intel Silicons. During PTL SOC Upstream, the common code changes are identified, and if any chnage is interdependent to PTL SOC recipe, we are keeping it aligned for recipe.
I apologize if this isn't clear, but this newly added API doesn't perform any critical boot blocking task that requires it to be called immediately. The purpose of this API is to dump QDF information during boot, and it was suggested that it be used to get this information from the report_platform file when showing the CPU information. As this is not a boot-critical feature, it doesn't need to be included in the PTL SOC upstream recipe at this time.
PTL SoC code review may take longer time but such smaller CL can be reviewed sooner and land immediately post review.
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