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Change subject: soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch replaces the SoC-specific config option
`SOC_INTEL_PANTHERLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
TEST=Able to build and boot google/fatcat without any functional impact
while debugging.
Change-Id: I36bbe14d02654ed9dbda21df0d9a6a6769b87754
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/pantherlake/Kconfig
1 file changed, 10 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/83962/1
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 5e5516a..e35233f 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -218,25 +218,18 @@
string "Location of FSP headers"
default "src/vendorcode/intel/fsp/fsp2_0/pantherlake/"
-config SOC_INTEL_PANTHERLAKE_DEBUG_CONSENT
- int "Debug Consent"
- # USB DBC is more common for developers so make this default to 4 if
- # SOC_INTEL_DEBUG_CONSENT=y
+# Override platform debug consent value:
+# 0:Disabled,
+# 2:Enabled Trace active: TraceHub is enabled and trace is active,
+# blocks s0ix,
+# 4:Enabled Trace ready: TraceHub is enabled and allowed S0ix,
+# 6:Enabled Trace power off: TraceHub is powergated, provide setting close to
+# functional low power state,
+# 7:user needs to configure Advanced Debug Settings manually.
+config SOC_INTEL_COMMON_DEBUG_CONSENT
+ int
default 4 if SOC_INTEL_DEBUG_CONSENT
default 0
- help
- This is to control debug interface on SOC.
- Setting non-zero value will allow to use DBC or DCI to debug SOC.
- PlatformDebugConsent in FspmUpd.h has the details.
-
- Desired platform debug type are
- 0:Disabled,
- 2:Enabled Trace active: TraceHub is enabled and trace is active,
- blocks s0ix,
- 4:Enabled Trace ready: TraceHub is enabled and allowed S0ix,
- 6:Enabled Trace power off: TraceHub is powergated, provide setting close to
- functional low power state,
- 7:user needs to configure Advanced Debug Settings manually.
config DATA_BUS_WIDTH
int
--
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Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
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Change subject: soc/intel/meteorlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/meteorlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch replaces the SoC-specific config option
`SOC_INTEL_METEORLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/rex0 without any functional impact
while debugging.
Change-Id: I657d20a38e15eee333a4e45c0c600736148173d4
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 6 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/83961/1
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 327b3a2..898bf21 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -357,21 +357,14 @@
depends on FSP_USE_REPO
default "3rdparty/fsp/MeteorLakeFspBinPkg/Fsp.fd"
-config SOC_INTEL_METEORLAKE_DEBUG_CONSENT
- int "Debug Consent for MTL"
- # USB DBC is more common for developers so make this default to 6 if
- # SOC_INTEL_DEBUG_CONSENT=y
+# Override platform debug consent value:
+# 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready,
+# 6:Enable Trace Power-Off, 7:Manual
+config SOC_INTEL_COMMON_DEBUG_CONSENT
+ int
default 6 if SOC_INTEL_DEBUG_CONSENT
default 2 if SOC_INTEL_COMMON_BLOCK_TRACEHUB
default 0
- help
- This is to control debug interface on SOC.
- Setting non-zero value will allow to use DBC or DCI to debug SOC.
- PlatformDebugConsent in FspmUpd.h has the details.
-
- Desired platform debug type are
- 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready,
- 6:Enable Trace Power-Off, 7:Manual
config DATA_BUS_WIDTH
int
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 055fec7..84e665d 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -364,7 +364,7 @@
const struct soc_intel_meteorlake_config *config)
{
/* Set debug probe type */
- m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_METEORLAKE_DEBUG_CONSENT;
+ m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT;
/* CrashLog config */
if (CONFIG(SOC_INTEL_CRASHLOG)) {
--
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Change subject: soc/intel/jasperlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/jasperlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch drops the SoC-specific config option
`SOC_INTEL_JASPERLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/dedede without any functional
impact while debugging.
Change-Id: I3e7abaf5fb3a0d5528041af5ce767a15fc738870
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/jasperlake/romstage/fsp_params.c
2 files changed, 1 insertion(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/83960/1
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 2871508..1502c75 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -192,22 +192,6 @@
config FSP_FD_PATH
default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd"
-config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT
- int "Debug Consent for JSL"
- # USB DBC is more common for developers so make this default to 3 if
- # SOC_INTEL_DEBUG_CONSENT=y
- default 3 if SOC_INTEL_DEBUG_CONSENT
- default 0
- help
- This is to control debug interface on SOC.
- Setting non-zero value will allow to use DBC or DCI to debug SOC.
- PlatformDebugConsent in FspmUpd.h has the details.
-
- Desired platform debug type are
- 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
- 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
- 6:Enable (2-wire DCI OOB), 7:Manual
-
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0x1400
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index 0132906..0299860 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -96,7 +96,7 @@
m_cfg->SmbusEnable = config->SmbusEnable;
/* Set debug probe type */
- m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_DEBUG_CONSENT;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT;
/* VT-d config */
m_cfg->VtdDisable = 0;
--
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Change subject: soc/intel/elkhartlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/elkhartlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch drops the SoC-specific config option
`SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot intel/elkhartlake_crb without any
functional impact while debugging.
Change-Id: Idb8db7230c432792e742218d41d891c529b2114f
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/romstage/fsp_params.c
2 files changed, 1 insertion(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/83959/1
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 42edbc6..815a7a1 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -240,22 +240,6 @@
Enable TSN GbE driver to provide board specific settings in the GBE MAC.
As an example of a possible change, the MAC address could be adjusted.
-config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT
- int "Debug Consent for EHL"
- # USB DBC is more common for developers so make this default to 3 if
- # SOC_INTEL_DEBUG_CONSENT=y
- default 3 if SOC_INTEL_DEBUG_CONSENT
- default 0
- help
- This is to control debug interface on SOC.
- Setting non-zero value will allow to use DBC or DCI to debug SOC.
- PlatformDebugConsent in FspmUpd.h has the details.
-
- Desired platform debug type are
- 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
- 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
- 6:Enable (2-wire DCI OOB), 7:Manual
-
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0x1400
diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c
index d85f291..cebc48d 100644
--- a/src/soc/intel/elkhartlake/romstage/fsp_params.c
+++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c
@@ -132,7 +132,7 @@
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
/* Set debug probe type */
- m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT;
/* TraceHub configuration */
if (is_devfn_enabled(PCH_DEVFN_TRACEHUB) && config->TraceHubMode) {
--
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Change subject: soc/intel/cannonlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/cannonlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch drops the SoC-specific config option
`SOC_INTEL_CANNONLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/hatch without any functional impact
while debugging.
Change-Id: Ifad11652b5fa6ff14f713f55a721cdbbfbfde471
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 1 insertion(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/83958/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 3aa06f4..d012dad 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -321,17 +321,6 @@
config FSP_FD_PATH_2
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Fsp.fd" if SOC_INTEL_COMETLAKE_1_2
-config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT
- int "Debug Consent for CNL"
- # USB DBC is more common for developers so make this default to 3 if
- # SOC_INTEL_DEBUG_CONSENT=y
- default 3 if SOC_INTEL_DEBUG_CONSENT
- default 0
- help
- This is to control debug interface on SOC.
- Setting non-zero value will allow to use DBC or DCI to debug SOC.
- PlatformDebugConsent in FspmUpd.h has the details.
-
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0xe00
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 2b25285..f0dd1c3 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -124,8 +124,7 @@
m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
/* Set debug probe type */
- m_cfg->PlatformDebugConsent =
- CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT;
/* Configure VT-d */
tconfig->VtdDisable = 0;
--
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Change subject: soc/intel/alderlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/alderlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch replaces the SoC-specific config option
`SOC_INTEL_ALDERLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/redrix without any functional impact
while debugging.
Change-Id: I9a9c81b72d707f5ed2e1a53c139ee22be0e30068
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 6 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/83957/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 632798e..8520439 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -426,20 +426,13 @@
default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_N && FSP_TYPE_IOT
-config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
- int "Debug Consent for ADL"
- # USB DBC is more common for developers so make this default to 2 if
- # SOC_INTEL_DEBUG_CONSENT=y
+# Override platform debug consent value:
+# 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power),
+# 7:Manual
+config SOC_INTEL_COMMON_DEBUG_CONSENT
+ int
default 2 if SOC_INTEL_DEBUG_CONSENT
default 0
- help
- This is to control debug interface on SOC.
- Setting non-zero value will allow to use DBC or DCI to debug SOC.
- PlatformDebugConsent in FspmUpd.h has the details.
-
- Desired platform debug type are
- 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power),
- 7:Manual
config DATA_BUS_WIDTH
int
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index a63b64c..b5e54f8 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -354,7 +354,7 @@
const struct soc_intel_alderlake_config *config)
{
/* Set debug probe type */
- m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT;
/* CrashLog config */
m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT);
--
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Change subject: soc/intel/cmn/basecode/debug: Add SOC_INTEL_COMMON_DEBUG_CONSENT config
......................................................................
soc/intel/cmn/basecode/debug: Add SOC_INTEL_COMMON_DEBUG_CONSENT config
This patch adds a generic config option, SOC_INTEL_COMMON_DEBUG_CONSENT,
to control the debug interface on Intel SoCs. This eliminates the need
for SoC-specific config options like SOC_INTEL_<SOC_NAME>_DEBUG_CONSENT.
Default values are provided for various debug types:
- 0: Disabled
- 1: Enabled (DCI OOB + [DbC])
- 2: Enabled (DCI OOB)
- 3: Enabled (USB3 DbC)
- 4: Enabled (XDP/MIPI60)
- 5: Enabled (USB2 DbC)
- 6: Enabled (2-wire DCI OOB)
- 7: Manual
Specific SoCs can override the SOC_INTEL_COMMON_DEBUG_CONSENT value
using SoC config override methods.
TEST=Able to build google/rex.
Change-Id: I84ad03f0ffe5da4bc53c665489c430fe9b65ede7
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/basecode/debug/Kconfig
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/83956/1
diff --git a/src/soc/intel/common/basecode/debug/Kconfig b/src/soc/intel/common/basecode/debug/Kconfig
index 759b969..af0a6b6 100644
--- a/src/soc/intel/common/basecode/debug/Kconfig
+++ b/src/soc/intel/common/basecode/debug/Kconfig
@@ -6,3 +6,19 @@
help
Driver to control runtime features of Intel SoC & coreboot. For example, controlling
the CSE firmware update feature without rebuilding the code.
+
+config SOC_INTEL_COMMON_DEBUG_CONSENT
+ int "Debug Consent for Intel SoC"
+ # USB DBC is more common for developers so make this default to 3 if
+ # SOC_INTEL_DEBUG_CONSENT=y
+ default 3 if SOC_INTEL_DEBUG_CONSENT
+ default 0
+ help
+ This is to control debug interface on SOC.
+ Setting non-zero value will allow to use DBC or DCI to debug SOC.
+ PlatformDebugConsent in FspmUpd.h has the details.
+
+ Desired platform debug type are
+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
+ 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
+ 6:Enable (2-wire DCI OOB), 7:Manual
\ No newline at end of file
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Change subject: src: Log boot info at early romstage
......................................................................
Patch Set 3:
(1 comment)
File src/cpu/intel/car/romstage.c:
https://review.coreboot.org/c/coreboot/+/83759/comment/21c2bf75_14cc07e2?us… :
PS3, Line 57: // Log boot information
Please use C89 comment style for consistency.
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/mediatek/mt8196: Enable mmu operation for L2C SRAM and DMA
......................................................................
Patch Set 8:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83925/comment/9f2c8cea_7672a539?us… :
PS8, Line 7: mmu
MMU
https://review.coreboot.org/c/coreboot/+/83925/comment/f109e360_39c8d5a0?us… :
PS8, Line 17: TEST=build pass
Any way to test it on hardware yet?
File src/soc/mediatek/mt8196/l2c_ops.c:
https://review.coreboot.org/c/coreboot/+/83925/comment/9ea1573a_1b9e7fff?us… :
PS8, Line 36: } while (((v >> CLUST_DIS_SHIFT) & CLUST_DIS_VAL) != CLUST_DIS_VAL);
Could this be an infinite loop, or is it guaranteed to finish?
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