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Change subject: soc/mediatek/mt8196: Enable mmu operation for L2C SRAM and DMA
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83925/comment/3615dc25_50298591?us… :
PS8, Line 16:
Please elaborate why the common implementation [1] can’t be used.
[1]: https://review.coreboot.org/c/coreboot/+/83937
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Change subject: soc/mediatek: Refactor mmu operation for L2C SRAM and DMA
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83937/comment/b90bb0be_52171bd1?us… :
PS5, Line 10: Move
*by* should be followed by:
moving, keeping
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Change subject: soc/mediatek/mt8196: Add NOR-Flash support
......................................................................
Patch Set 5:
(1 comment)
File src/soc/mediatek/mt8196/spi.c:
https://review.coreboot.org/c/coreboot/+/83923/comment/55defe1f_fc0c2350?us… :
PS5, Line 33: void mtk_snfc_init(void)
: {
: const struct pad_func *ptr;
:
: for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) {
: ptr = &nor_pinmux[i];
:
: gpio_set_pull(ptr->gpio, GPIO_PULL_ENABLE, ptr->select);
: gpio_set_mode(ptr->gpio, ptr->func);
:
: if (gpio_set_driving(ptr->gpio, GPIO_DRV_14_MA) < 0)
: printk(BIOS_ERR,
: "%s: failed to set pin drive to 14 mA for %d\n",
: __func__, ptr->gpio.id);
: else
: printk(BIOS_DEBUG, "%s: got pin drive: %#x\n", __func__,
: gpio_get_driving(ptr->gpio));
: }
: }
Looks quite similar to the implementation in `src/soc/mediatek/mt8188/spi.c`. Make it more similar or improve the implementation there? The only difference is `GPIO_DRV_14_MA` vs. `GPIO_DRV_8_MA`.
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Change subject: soc/mediatek/mt8196: Add NOR-Flash support
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83923/comment/e3a20e3d_adefd657?us… :
PS5, Line 11: TEST=read nor flash data successfully.
Any benchmark data for the record?
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Change subject: soc/mediatek/mt8196: Add GPIO driver
......................................................................
Patch Set 4:
(3 comments)
File src/soc/mediatek/mt8196/gpio.c:
https://review.coreboot.org/c/coreboot/+/83922/comment/f1c5fe78_a980bf71?us… :
PS4, Line 393: return NULL;
Log an error?
https://review.coreboot.org/c/coreboot/+/83922/comment/fc270af6_fe2e5d74?us… :
PS4, Line 400: return NULL;
Ditto.
File src/soc/mediatek/mt8196/include/soc/gpio_base.h:
PS4:
It’s identical to `src/soc/mediatek/mt8195/include/soc/gpio_base.h`.
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63552?usp=email )
(
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
......................................................................
mb/google/brya: Reset XHCI controller while preparing for S5
This patch calls `xhci_host_reset()` function to perform XHCI
controller reset.
Currently, the PMC IPC times out while sending the USB-C (0xA7) command
during poweron from S5 (S5->S4->S3->S0).
On Brya variants, poweron from S5 state results in PMC error while
sending PMC IPC (0xA7) to USB-C active ports, log here:
localhost ~ # cbmem -c | grep ERROR
[ERROR] Â PMC IPC timeout after 1000 ms
[ERROR] Â PMC IPC command 0x200a7 failed
[ERROR] Â pmc_send_ipc_cmd failed
[ERROR] Â Failed to setup port:0 to initial state
[ERROR] Â PMC IPC timeout after 1000 ms
[ERROR] Â PMC IPC command 0x200a7 failed
[ERROR] Â pmc_send_ipc_cmd failed
[ERROR] Â Failed to setup port:1 to initial state
[ERROR] Â PMC IPC timeout after 1000 ms
[ERROR] Â PMC IPC command 0x20a0 failed
This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0).
During poweron the state of USB ports are not the same between S5 and G3
and it appears that the active USB port still is in U3 (suspend) while
PMC tries to send the IPC command, which results in a timeout.
This patch utilises the S5 SMI handler to reset the XHCI controller
using `xhci_host_reset()` prior entering into the S5, it helps to
restore the port state to active hence, no PMC timeout is seen with
this code change.
Supporting Doc=Intel expected to release a TA (Technical Advisory)
document to acknowledge this observation and supported W/A for ADL
generation platforms.
Till that time, keeping this W/A as part of the google/brya specific
mainboard alone.
Note: other ADL-SoC based mainboards might need to apply the similar
W/A.
BUG=b:227289581
TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7)
during resume from S5.
Total Time: 1,045,855
localhost ~ # cbmem -c | grep ERROR
No PMC timeout error is observed with this CL.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63552
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brya/smihandler.c
1 file changed, 8 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, approved
diff --git a/src/mainboard/google/brya/smihandler.c b/src/mainboard/google/brya/smihandler.c
index 9208d51..2adc62b 100644
--- a/src/mainboard/google/brya/smihandler.c
+++ b/src/mainboard/google/brya/smihandler.c
@@ -1,15 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <elog.h>
#include <intelblocks/smihandler.h>
+#include <intelblocks/xhci.h>
#include <variant/ec.h>
void mainboard_smi_sleep(u8 slp_typ)
{
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
+ /*
+ * Workaround: Reset the XHCI controller prior to S5 to avoid
+ * PMC timeout error during poweron from S5.
+ */
+ if (slp_typ == ACPI_S5)
+ xhci_host_reset();
}
int mainboard_smi_apmc(u8 apmc)
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Attention is currently required from: Kapil Porwal, Pranava Y N, Saurabh Mishra.
Hello Kapil Porwal, Pranava Y N, Saurabh Mishra, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified-1 by build bot (Jenkins)
Change subject: soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch replaces the SoC-specific config option
`SOC_INTEL_PANTHERLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
TEST=Able to build and boot google/fatcat without any functional impact
while debugging.
Change-Id: I36bbe14d02654ed9dbda21df0d9a6a6769b87754
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/pantherlake/Kconfig
1 file changed, 9 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/83962/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: soc/intel/cmn/basecode/debug: Add SOC_INTEL_COMMON_DEBUG_CONSENT config
......................................................................
soc/intel/cmn/basecode/debug: Add SOC_INTEL_COMMON_DEBUG_CONSENT config
This patch adds a generic config option, SOC_INTEL_COMMON_DEBUG_CONSENT,
to control the debug interface on Intel SoCs. This eliminates the need
for SoC-specific config options like SOC_INTEL_<SOC_NAME>_DEBUG_CONSENT.
Default values are provided for various debug types:
- 0: Disabled
- 1: Enabled (DCI OOB + [DbC])
- 2: Enabled (DCI OOB)
- 3: Enabled (USB3 DbC)
- 4: Enabled (XDP/MIPI60)
- 5: Enabled (USB2 DbC)
- 6: Enabled (2-wire DCI OOB)
- 7: Manual
Specific SoCs can override the SOC_INTEL_COMMON_DEBUG_CONSENT value
using SoC config override methods.
TEST=Able to build google/rex.
Change-Id: I84ad03f0ffe5da4bc53c665489c430fe9b65ede7
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/basecode/debug/Kconfig
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/83956/2
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Change subject: soc/intel/tigerlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/tigerlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch drops the SoC-specific config option
`SOC_INTEL_TIGERLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/volteer without any functional
impact while debugging.
Change-Id: I3e96b20e7e8b3ce3c2e4884abd315a5cc55fe71d
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 1 insertion(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/83963/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 59f54aa..77e53ad 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -253,22 +253,6 @@
default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Fsp.fd" if FSP_TYPE_IOT
default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Fsp.fd" if FSP_TYPE_CLIENT
-config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT
- int "Debug Consent for TGL"
- # USB DBC is more common for developers so make this default to 3 if
- # SOC_INTEL_DEBUG_CONSENT=y
- default 3 if SOC_INTEL_DEBUG_CONSENT
- default 0
- help
- This is to control debug interface on SOC.
- Setting non-zero value will allow to use DBC or DCI to debug SOC.
- PlatformDebugConsent in FspmUpd.h has the details.
-
- Desired platform debug type are
- 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
- 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
- 6:Enable (2-wire DCI OOB), 7:Manual
-
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0x2000
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index f7337f0..00b5315 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -130,7 +130,7 @@
/* Enable SMBus controller based on config */
m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
/* Set debug probe type */
- m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT;
/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
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