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Change subject: soc/intel/cmn/basecode/debug: Add SOC_INTEL_COMMON_DEBUG_CONSENT config
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Patch Set 2: Code-Review+2
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Change subject: acpi: Move HPET generation to a common location
......................................................................
Patch Set 13:
(1 comment)
File src/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/76128/comment/310703cd_9ad4c0f0?us… :
PS13, Line 134: depends on HAVE_ACPI_TABLES
> +1
Actually, maybe even with an additional inverse Kconfig `NO_HPET` and then `default !NO_HPET`.
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Change subject: acpi: Move HPET generation to a common location
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Patch Set 13:
(1 comment)
File src/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/76128/comment/57a94863_f240a6df?us… :
PS13, Line 134: depends on HAVE_ACPI_TABLES
> i wonder if it would be better to have a HAVE_HPET Kconfog option to arch/x86/Kconfig and use that a […]
+1
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Change subject: acpi: Move HPET generation to a common location
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Patch Set 13:
(1 comment)
File src/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/76128/comment/75fd0774_48b473f2?us… :
PS13, Line 134: depends on HAVE_ACPI_TABLES
> It would warn, but I'm surprised (after testing this) that the return code is still 0.
i wonder if it would be better to have a HAVE_HPET Kconfog option to arch/x86/Kconfig and use that as condition in acpi/Makefile.mk. then we can drop the whole ACPI_HPET option and don't have to deal with the depends on HAVE_ACPI_TABLES thing and the ACPI table will still only be generated when HAVE_ACPI_TABLES is set due to how things are done in acpi/Makefile.mk
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Change subject: mb/goog/rex: unlock gpio wake sources
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Able to test touchpad and finger print modules wake working with this CL on all Rex variants.
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Change subject: util/nixshell: fix devshell for some payloads
......................................................................
Patch Set 1:
(1 comment)
File util/nixshell/devshell-i386.nix:
https://review.coreboot.org/c/coreboot/+/82943/comment/3f61f35a_3d8ede34?us… :
PS1, Line 24: gnat # Fix https://github.com/NixOS/nixpkgs/issues/142943 for EDK2
> ```
> make -s tbuild [/home/9l/src-git9l/coreboot/payloads/external/edk2/workspace/Build/UefiPayloadPkgX64/RELEASE_COREBOOT/X64/CryptoPkg/Library/OpensslLib/OpensslLib]
> ```
If that command failed, I suggest looking into the output of that command.
I'm not very familiar with nix, but to me the fix seems to be more of a side
effect, i.e. something not Ada related that `gnat` pulls in as dependency maybe?
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Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 45:
(1 comment)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/70dfba2b_a35f11e8?us… :
PS17, Line 54: .port = PID_GPIOCOM0,
> in MTL, we have:
>
> IOM_AUX_ORI_BIAS_CTRL_PUP[0] 0x1070
> 7:0 RW 0x0 GROUP_ID Group ID in PCH GPIO
> 10:8 RW 0x0 BIT_NUM Data bit Position in PCH GPIO
> 23:16 RW 0x0 VW_INDEX VW Index in PCH GPIO
In that case, all you need to do is submit a new Kconfig to support 16-bit CPU ports. You will need to specify SEGMENTID_CHIPSET0 in one more Kconfig, which may be SoC-specific. Then, before creating the PTL GPIO CL, add support for new 16-bit CPU port IDs in the tcss.c code.
The GPIO CL for PTL will simply add the CPU port number in the same way as MTL and other SoCs. The only thing that sets it apart is the new Kconfig that adds 16-bit support.
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