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I'd like you to reexamine a change. Please visit
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Change subject: mb/goog/{brya/brox/rex}: unlock gpio wake sources
......................................................................
mb/goog/{brya/brox/rex}: unlock gpio wake sources
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up
after it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=firmware-brya-14505.B
TEST=verify brask, brya, brox, or rex DUT is able to power down and stay
powered down when selecting the "Power off" button in the firmware dev
screen.
Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brox/variants/jubilant/gpio.c
M src/mainboard/google/brox/variants/lotso/gpio.c
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
M src/mainboard/google/brya/variants/orisa/gpio.c
M src/mainboard/google/brya/variants/trulo/gpio.c
6 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/83949/6
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Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Reka Norman, Rishika Raj, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: mb/goog/{brya/brox/rex}: unlock gpio wake sources
......................................................................
mb/goog/{brya/brox/rex}: unlock gpio wake sources
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up
after it's been powered off from the firmware dev screen.
BUG=b:360380950
BRANCH=firmware-brya-14505.B
TEST=verify brask, brya, brox, or rex DUT is able to power down and stay
powered down when selecting the "Power off" button in the firmware dev
screen.
Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brox/variants/jubilant/gpio.c
M src/mainboard/google/brox/variants/lotso/gpio.c
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
M src/mainboard/google/brya/variants/orisa/gpio.c
M src/mainboard/google/brya/variants/trulo/gpio.c
6 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/83949/5
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/goog/{brya/brox/rex}: unlock gpio wake sources
......................................................................
mb/goog/{brya/brox/rex}: unlock gpio wake sources
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up
after it's been powered off from the firmware dev screen.
BUG=b:360380950
BRANCH=firmware-brya-14505.B
TEST=verify brask, brya, brox, or rex DUT is able to power down and stay powered down when selecting the "Power off" button in the firmware dev screen.
Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brox/variants/jubilant/gpio.c
M src/mainboard/google/brox/variants/lotso/gpio.c
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
M src/mainboard/google/brya/variants/orisa/gpio.c
M src/mainboard/google/brya/variants/trulo/gpio.c
6 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/83949/4
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Change subject: mb/goog/{brya/brox/rex}: unlock gpio wake sources
......................................................................
Patch Set 3:
This change is ready for review.
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Nicholas Sudsgaard has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/80333?usp=email )
Change subject: device/azalia: Rework azalia verb tables
......................................................................
Patch Set 9:
(4 comments)
This change is ready for review.
Patchset:
PS5:
> Did some quick tests on compiler explorer and it seems like using pointers can cut down the instruct […]
Instruction count is not that important. Using pointers to avoid stack overflows, as this struct is quite big.
File src/include/device/azalia_device.h:
https://review.coreboot.org/c/coreboot/+/80333/comment/63e65bae_2660ebfe?us… :
PS2, Line 21: #define HDA_MAX_CORBSIZE 256
> Not sure when to use the HDA_ prefix and the AZALIA_ prefix.
Not relevant for new patchset.
File src/include/device/azalia_table_exporter.c:
https://review.coreboot.org/c/coreboot/+/80333/comment/c5eca2a3_3b945ee5?us… :
PS7, Line 20:
> This file is assumed to be #included at the end of mainboard hda_verb.c. […]
Thanks for pointing that out! `mainboard_azalia_program_runtime_verbs` should work fine without any modifications in the new patchset (tested a simple function).
File src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/80333/comment/812ad63a_0da9834a?us… :
PS7, Line 10: 0
> How about adding another attribute for the codec number to the struct? So it's not repeated over and […]
I have experimented with that, but I'm not sure how to do that without adding some code to runtime. There are some benefits to moving all the verb initialization to runtime (similar to `init` of `chip_operations`).
- No need to repeat the codec address. Though, it would look like `AZALIA_PIN_CFG(codec, 0x0a, 0x40f000f0)` instead.
- `verb_count` can be set automatically
- AFAIK there is no benefits using macros for `AZALIA_VERB_12B` etc... we can change those to inline functions for some type safety?
- `AZALIA_SUBVENDOR` can be set automatically (`AZALIA_RESET` as well?)
- A separate `mainboard_azalia_program_runtime_verbs` is not needed
You could still add the values directly into `.verbs` if you really need that performance.
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Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik.
Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83949?usp=email
to look at the new patch set (#2).
Change subject: mb/goog/brya: unlock gpio wake sources
......................................................................
mb/goog/brya: unlock gpio wake sources
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950
BRANCH=firmware-brya-14505.B
TEST=verify brask or brya DUT is able to power down and stay powered
down when selecting the "Power off" button in the firmware dev screen.
Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
M src/mainboard/google/brya/variants/orisa/gpio.c
M src/mainboard/google/brya/variants/trulo/gpio.c
4 files changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/83949/2
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Cliff Huang has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 46:
(1 comment)
File src/soc/intel/pantherlake/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/3d0d4083_59c66f8a?us… :
PS23, Line 5: INTC1041
> > got it. I will change these to the following: […]
Subrata, np. My understanding now is that we should have this .h file instead of acpi/dptf.asl. This soc/dptf.h can be included to override the SOC-specific values for dft manager/generic/fan defines in soc/intel/common/acpi/dptf_common.asl. soc/dptf.h can be included in mb dsdt.asl. In addition, soc/dptf.h is used in dptf drivers for the same. If this is correct, we can create just soc/dptf.h and remove acpi/dptf.asl, since it won't be used at all.
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Hello Subrata Banik, build bot (Jenkins),
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Change subject: soc/intel/common/block/cpu: Use the effective way size for NEM+
......................................................................
soc/intel/common/block/cpu: Use the effective way size for NEM+
The Last Level Cache (LLC) way size (or sets) is not necessarily a
power of two. However, on some platforms, the effective way size, the
way size which should be considered for No-Eviction Mode (NEM)
purposes is the biggest power of two of the way size.
Alder Lake External Design Specification #627270 "3.5.2 No-Eviction
Mode (NEM) Sizes" provides some understanding that the maximum NEM
size depends on the number of CBO which used to be accessible via MSR
0x396. Unfortunately, this MSR is not available and as a general
implementation the recommendation is to use the biggest power of two
of the way size instead.
The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' has been
introduced to control this behavior.
BUG=b:360332771
TEST=Verified on rex
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83946/4
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj, Subrata Banik, Tarun,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83947?usp=email
to look at the new patch set (#4).
Change subject: soc/intel: Use NEM+ effective way size for the right platforms
......................................................................
soc/intel: Use NEM+ effective way size for the right platforms
Alder Lake, Meteor Lake and Panther Lake uses the effective way size
when setting up the Enhanced No-Eviction
Mode (cf. `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE').
BUG=b:360332771
TEST=Verified on rex
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/pantherlake/Kconfig
3 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/83947/4
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