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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#16).
Change subject: mb/asrock: Add Asrock Industrial IMB-1222 motherboard
......................................................................
mb/asrock: Add Asrock Industrial IMB-1222 motherboard
ASRock IMB-1222 Intel Comet Lake-S Q470E industrial thin mini-ITX
motherboard [1,2].
Working:
- Dual Channel DDR4 2933/2666/2400 MHz;
- Intel UHD Graphics (VGA Option ROM, libgfxinit);
- DP (both), HDMI;
- PCIe x16 Slot (Gen3);
- SATA ports;
- USB 2.0 ports;
- USB 3.0 ports;
- M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi);
- M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1);
- M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3);
- LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps;
- LAN2 Intel I219LM, 10/100/1000 Mbps;
- Realtek ALC887 HD Audio (line-out, mic-in);
- COM 1/2/3/4 ports;
- onboard speaker;
- HWM/FANs control (fintek f81966);
- S3 suspend and wake;
- TPM;
- disabling ME (me_cleaner);
- boots Ubuntu 22.04/24.04 (SeaBIOS, Linuxboot, edk2 [2]).
Unknown/untested:
- USB3.0 in M.2 Key-B 3042/3052 slot;
- eDP/LVDS;
- PCIe riser cards;
- SPDIF.
Known issues:
- there is no video output in firmware with edk2 [2],
- incorrect fmap.fmd: boot fails at bootblock.
There is no schematic/boardview, reverse engineering only.
This port is based on system76/bonw14 because it has a similar topology.
[1] https://www.asrockind.com/en-gb/IMB-1222https://web.archive.org/web/20220924171403/https://www.asrockind.com/
en-gb/IMB-1222
[2] MrChromebox' edk2 fork, https://github.com/mrchromebox/edk2
uefipayload_202309 branch
Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
A Documentation/mainboard/asrock/imb-1222.md
M Documentation/mainboard/index.md
A src/mainboard/asrock/imb-1222/Kconfig
A src/mainboard/asrock/imb-1222/Kconfig.name
A src/mainboard/asrock/imb-1222/Makefile.mk
A src/mainboard/asrock/imb-1222/acpi/mainboard.asl
A src/mainboard/asrock/imb-1222/acpi/sleep.asl
A src/mainboard/asrock/imb-1222/board_info.txt
A src/mainboard/asrock/imb-1222/bootblock.c
A src/mainboard/asrock/imb-1222/cmos.default
A src/mainboard/asrock/imb-1222/cmos.layout
A src/mainboard/asrock/imb-1222/data.vbt
A src/mainboard/asrock/imb-1222/devicetree.cb
A src/mainboard/asrock/imb-1222/dsdt.asl
A src/mainboard/asrock/imb-1222/fmap.fmd
A src/mainboard/asrock/imb-1222/gma-mainboard.ads
A src/mainboard/asrock/imb-1222/gpio.c
A src/mainboard/asrock/imb-1222/gpio_beep.c
A src/mainboard/asrock/imb-1222/hda_verb.c
A src/mainboard/asrock/imb-1222/include/mainboard/gpio.h
A src/mainboard/asrock/imb-1222/include/mainboard/superio.h
A src/mainboard/asrock/imb-1222/panic.c
A src/mainboard/asrock/imb-1222/ramstage.c
A src/mainboard/asrock/imb-1222/romstage.c
A src/mainboard/asrock/imb-1222/superio.c
25 files changed, 1,247 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83107/16
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Change subject: soc/intel/tigerlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS3:
ah, pantherlake is the soc that's currently being brought upstream, so that option isn't used anywhere yet. i'll assume that the soc-specific code populating the corresponding fsp upd has been updated or will be updated too, so that those parts still match
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83962/comment/1b2c6678_0913b2d5?us… :
PS3, Line 231: default 0
same question as on adl and mtl
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Change subject: soc/intel/meteorlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83961/comment/fc5680e3_266394bd?us… :
PS2, Line 367: default 0
same question about the duplicated default 0 as on the alderlake change
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Change subject: soc/intel/alderlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83957/comment/0439b9bd_2410d194?us… :
PS2, Line 435: default 0
> the default 0 line is probably unneeded, since that's also the default in the basecode kconfig in th […]
i mean it doesn't hurt to keep that one, but would be good if you can have a quick look at this and decide on whether to keep that duplicate default 0 or not; i don't have a too strong opinion on this, so i'd be fine with this just marked as resolved
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Change subject: soc/intel/jasperlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/elkhartlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
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Patch Set 2: Code-Review+2
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Change subject: soc/intel/cannonlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/alderlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83957/comment/dba9967d_a213c06a?us… :
PS2, Line 435: default 0
the default 0 line is probably unneeded, since that's also the default in the basecode kconfig in the case that SOC_INTEL_DEBUG_CONSENT isn't selected and only the case that SOC_INTEL_DEBUG_CONSENT is selected needs to be overridden to keep the current behavior
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Change subject: soc/intel/cmn/basecode/debug: Add SOC_INTEL_COMMON_DEBUG_CONSENT config
......................................................................
soc/intel/cmn/basecode/debug: Add SOC_INTEL_COMMON_DEBUG_CONSENT config
This patch adds a generic config option, SOC_INTEL_COMMON_DEBUG_CONSENT,
to control the debug interface on Intel SoCs. This eliminates the need
for SoC-specific config options like SOC_INTEL_<SOC_NAME>_DEBUG_CONSENT.
Default values are provided for various debug types:
- 0: Disabled
- 1: Enabled (DCI OOB + [DbC])
- 2: Enabled (DCI OOB)
- 3: Enabled (USB3 DbC)
- 4: Enabled (XDP/MIPI60)
- 5: Enabled (USB2 DbC)
- 6: Enabled (2-wire DCI OOB)
- 7: Manual
Specific SoCs can override the SOC_INTEL_COMMON_DEBUG_CONSENT value
using SoC config override methods.
TEST=Able to build google/rex.
Change-Id: I84ad03f0ffe5da4bc53c665489c430fe9b65ede7
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83956
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Reviewed-by: Eric Lai <ericllai(a)google.com>
---
M src/soc/intel/common/basecode/debug/Kconfig
1 file changed, 16 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
diff --git a/src/soc/intel/common/basecode/debug/Kconfig b/src/soc/intel/common/basecode/debug/Kconfig
index 759b969..00a03d8 100644
--- a/src/soc/intel/common/basecode/debug/Kconfig
+++ b/src/soc/intel/common/basecode/debug/Kconfig
@@ -6,3 +6,19 @@
help
Driver to control runtime features of Intel SoC & coreboot. For example, controlling
the CSE firmware update feature without rebuilding the code.
+
+config SOC_INTEL_COMMON_DEBUG_CONSENT
+ int "Debug Consent for Intel SoC"
+ # USB DBC is more common for developers so make this default to 3 if
+ # SOC_INTEL_DEBUG_CONSENT=y
+ default 3 if SOC_INTEL_DEBUG_CONSENT
+ default 0
+ help
+ This is to control debug interface on SOC.
+ Setting non-zero value will allow to use DBC or DCI to debug SOC.
+ PlatformDebugConsent in FspmUpd.h has the details.
+
+ Desired platform debug type are
+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
+ 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
+ 6:Enable (2-wire DCI OOB), 7:Manual.
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