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Change subject: soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/intel/meteorlake/chip.h: Use boolean type where applicable
......................................................................
soc/intel/meteorlake/chip.h: Use boolean type where applicable
Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd
Signed-off-by: Michael Strosche <michael.strosche(a)gmail.com>
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77374
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/soc/intel/meteorlake/chip.h
1 file changed, 37 insertions(+), 34 deletions(-)
Approvals:
Eric Lai: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index b75cbba..e76f169 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -16,6 +16,7 @@
#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/usb.h>
+#include <stdbool.h>
#include <stdint.h>
/* Define config parameters for In-Band ECC (IBECC). */
@@ -165,17 +166,17 @@
uint32_t gen4_dec;
/* Enable S0iX support */
- int s0ix_enable;
+ bool s0ix_enable;
/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
- uint8_t tcss_d3_hot_disable;
+ bool tcss_d3_hot_disable;
/* Enable DPTF support */
- int dptf_enable;
+ bool dptf_enable;
/* Deep SX enable for both AC and DC */
- int deep_s3_enable_ac;
- int deep_s3_enable_dc;
- int deep_s5_enable_ac;
- int deep_s5_enable_dc;
+ bool deep_s3_enable_ac;
+ bool deep_s3_enable_dc;
+ bool deep_s5_enable_ac;
+ bool deep_s5_enable_dc;
/* Deep Sx Configuration
* DSX_EN_WAKE_PIN - Enable WAKE# pin
@@ -208,8 +209,8 @@
SAGV_POINTS_0_1_2_3 = 0x0f,
} sagv_wp_bitmap;
- /* Rank Margin Tool. 1:Enable, 0:Disable */
- uint8_t rmt;
+ /* Rank Margin Tool. true:Enable, false:Disable */
+ bool rmt;
/* USB related */
struct usb2_port_config usb2_ports[CONFIG_SOC_INTEL_USB2_DEV_MAX];
@@ -225,21 +226,21 @@
/* SATA related */
uint8_t sata_mode;
- uint8_t sata_salp_support;
- uint8_t sata_ports_enable[8];
- uint8_t sata_ports_dev_slp[8];
+ bool sata_salp_support;
+ bool sata_ports_enable[8];
+ bool sata_ports_dev_slp[8];
/*
- * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
- * Default 0. Setting this to 1 disables the SATA Power Optimizer.
+ * Enable(false)/Disable(true) SATA Power Optimizer on PCH side.
+ * Default false. Setting this to true disables the SATA Power Optimizer.
*/
- uint8_t sata_pwr_optimize_disable;
+ bool sata_pwr_optimize_disable;
/*
* SATA Port Enable Dito Config.
* Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
*/
- uint8_t sata_ports_enable_dito_config[8];
+ bool sata_ports_enable_dito_config[8];
/* SataPortsDmVal is the DITO multiplier. Default is 15. */
uint8_t sata_ports_dm_val[8];
@@ -247,8 +248,8 @@
uint16_t sata_ports_dito_val[8];
/* Audio related */
- uint8_t pch_hda_audio_link_hda_enable;
- uint8_t pch_hda_dsp_enable;
+ bool pch_hda_audio_link_hda_enable;
+ bool pch_hda_dsp_enable;
bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
@@ -294,10 +295,11 @@
IGD_SM_56MB = 0xFD,
IGD_SM_60MB = 0xFE,
} igd_dvmt50_pre_alloc;
- uint8_t skip_ext_gfx_scan;
- /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
- uint8_t eist_enable;
+ bool skip_ext_gfx_scan;
+
+ /* Enable/Disable EIST. true:Enabled, false:Disabled */
+ bool eist_enable;
/*
* When enabled, this feature makes the SoC throttle when the power
@@ -445,16 +447,16 @@
uint8_t cpu_ratio_override;
/*
- * Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
- * Default 0. Setting this to 1 disables the DMI Power Optimizer.
+ * Enable(true)/Disable(false) DMI Power Optimizer on PCH side.
+ * Default false. Setting this to true disables the DMI Power Optimizer.
*/
- uint8_t dmi_pwr_optimize_disable;
+ bool dmi_pwr_optimize_disable;
/*
- * Enable(1)/Disable(0) CPU Replacement check.
- * Default 0. Setting this to 1 to check CPU replacement.
+ * Enable(true)/Disable(false) CPU Replacement check.
+ * Default false. Setting this to true to check CPU replacement.
*/
- uint8_t cpu_replacement_check;
+ bool cpu_replacement_check;
/* ISA Serial Base selection. */
enum {
@@ -472,7 +474,8 @@
* Enable or Disable C1 C-state Auto Demotion & un-demotion
* The algorithm looks at the behavior of the wake up tracker, how
* often it is waking up, and based on that it demote the c-state.
- * Default 0. Set this to 1 in order to disable C1-state auto demotion.
+ * Default false. Set this to true in order to disable C1-state auto
+ * demotion.
* NOTE: Un-Demotion from Demoted C1 needs to be disabled when
* C1 C-state Auto Demotion is disabled.
*/
@@ -480,8 +483,8 @@
/*
* Enable or Disable Package C-state Demotion.
- * Default is set to 0.
- * Set this to 1 in order to disable Package C-state demotion.
+ * Default is set to false.
+ * Set this to true in order to disable Package C-state demotion.
* NOTE: Un-Demotion from demoted Package C-state needs to be disabled
* when auto demotion is disabled.
*/
@@ -507,8 +510,8 @@
/*
* Enable or Disable Reduced BasicMemoryTest size.
- * Default is set to 0.
- * Set this to 1 in order to reduce BasicMemoryTest size
+ * Default is set to false.
+ * Set this to true in order to reduce BasicMemoryTest size
*/
bool lower_basic_mem_test_size;
@@ -519,9 +522,9 @@
uint16_t psys_pl2_watts;
/* Enable or Disable Acoustic Noise Mitigation feature */
- uint8_t enable_acoustic_noise_mitigation;
+ bool enable_acoustic_noise_mitigation;
/* Disable Fast Slew Rate for Deep Package C States for VR domains */
- uint8_t disable_fast_pkgc_ramp[NUM_VR_DOMAINS];
+ bool disable_fast_pkgc_ramp[NUM_VR_DOMAINS];
/*
* Slew Rate configuration for Deep Package C States for VR domains
* as per `enum slew_rate` data type.
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Change subject: soc/intel/alderlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83957/comment/7d91284d_40a222ba?us… :
PS2, Line 435: default 0
> i mean it doesn't hurt to keep that one, but would be good if you can have a quick look at this and […]
Acknowledged
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Change subject: soc/intel/meteorlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/meteorlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch replaces the SoC-specific config option
`SOC_INTEL_METEORLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/rex0 without any functional impact
while debugging.
Change-Id: I657d20a38e15eee333a4e45c0c600736148173d4
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 6 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/83961/3
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Change subject: soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch replaces the SoC-specific config option
`SOC_INTEL_PANTHERLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
TEST=Able to build and boot google/fatcat without any functional impact
while debugging.
Change-Id: I36bbe14d02654ed9dbda21df0d9a6a6769b87754
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---
M src/soc/intel/pantherlake/Kconfig
1 file changed, 9 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/83962/4
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Change subject: soc/intel/alderlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
soc/intel/alderlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
This patch replaces the SoC-specific config option
`SOC_INTEL_ALDERLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
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Change-Id: I9a9c81b72d707f5ed2e1a53c139ee22be0e30068
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 6 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/83957/3
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Change subject: soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENT
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> ah, pantherlake is the soc that's currently being brought upstream, so that option isn't used anywhere yet. i'll assume that the soc-specific code populating the corresponding fsp upd has been updated or will be updated too, so that those parts still match
yes, it will be updated as and when FSP header are in public.
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