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Change subject: mb/asrock: Add Asrock Industrial IMB-1222 motherboard
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Set Ready For Review
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Change subject: soc/mediatek/mt8196: Add NOR-Flash support
......................................................................
Patch Set 8:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83923/comment/0355eee9_04b0bb8d?us… :
PS5, Line 11: TEST=read nor flash data successfully.
> How do you know, if the driver fully works then? (Anyway, feel free to ignore and mark as resolved. […]
Done
File src/soc/mediatek/mt8196/spi.c:
https://review.coreboot.org/c/coreboot/+/83923/comment/d2fb20d6_0094711a?us… :
PS5, Line 33: void mtk_snfc_init(void)
: {
: const struct pad_func *ptr;
:
: for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) {
: ptr = &nor_pinmux[i];
:
: gpio_set_pull(ptr->gpio, GPIO_PULL_ENABLE, ptr->select);
: gpio_set_mode(ptr->gpio, ptr->func);
:
: if (gpio_set_driving(ptr->gpio, GPIO_DRV_14_MA) < 0)
: printk(BIOS_ERR,
: "%s: failed to set pin drive to 14 mA for %d\n",
: __func__, ptr->gpio.id);
: else
: printk(BIOS_DEBUG, "%s: got pin drive: %#x\n", __func__,
: gpio_get_driving(ptr->gpio));
: }
: }
> I agree that part of the code (and the `pad_func` struct) can be moved to the common code (but of co […]
please review here CL:83989
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Change subject: soc/mediatek/mt8196: Enable MMU operation for L2C SRAM and DMA
......................................................................
Patch Set 12:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83925/comment/dfaf3f2e_fc0b6974?us… :
PS8, Line 7: mmu
> MMU
Done
https://review.coreboot.org/c/coreboot/+/83925/comment/5287ef83_90ee129b?us… :
PS8, Line 16:
> Please elaborate why the common implementation [1] can’t be used. […]
because the disable cache flow is different from the previous chips.
https://review.coreboot.org/c/coreboot/+/83925/comment/f501c3c1_14e48313?us… :
PS8, Line 17: TEST=build pass
> Any way to test it on hardware yet?
Done
File src/soc/mediatek/mt8196/l2c_ops.c:
https://review.coreboot.org/c/coreboot/+/83925/comment/cd08872c_f6a26ad7?us… :
PS8, Line 36: } while (((v >> CLUST_DIS_SHIFT) & CLUST_DIS_VAL) != CLUST_DIS_VAL);
> Could this be an infinite loop, or is it guaranteed to finish?
will finish, verified
File src/soc/mediatek/mt8196/l2c_ops.c:
https://review.coreboot.org/c/coreboot/+/83925/comment/b0fc0e52_4e682781?us… :
PS10, Line 11: FULLnHALF
> UPPER_CASE please.
Done
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Hello Hung-Te Lin, Xi Chen, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83925?usp=email
to look at the new patch set (#12).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: soc/mediatek/mt8196: Enable MMU operation for L2C SRAM and DMA
......................................................................
soc/mediatek/mt8196: Enable MMU operation for L2C SRAM and DMA
- Turn off L2C SRAM and reconfigure as L2 cache:
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
- Configure DMA buffer in DRAM:
Set DRAM DMA to be non-cacheable to load blob correctly.
TEST=build pass, register(disable_l2c) read ok
BUG=b:317009620
Change-Id: I6a3cb63d3418f085f5d8d08b282dd59ea431c294
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/l2c_ops.c
M src/soc/mediatek/mt8196/soc.c
3 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83925/12
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