Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83955?usp=email )
Change subject: soc/intel/elkhartlake: Select SOC_INTEL_COMMON_BASECODE
......................................................................
soc/intel/elkhartlake: Select SOC_INTEL_COMMON_BASECODE
This patch selects the SOC_INTEL_COMMON_BASECODE option for Elkhart
Lake so that future patches can incorporate the common code debug
feature with it.
TEST=Able to build the EHL platform.
Change-Id: I71d95352fe627a7f1912f802aa971ad1ebbbead7
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83955
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/intel/elkhartlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 58c4556..42edbc6 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -30,6 +30,7 @@
select PMC_GLOBAL_RESET_ENABLE_LOCK
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_BASECODE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
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Felix Held has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83955?usp=email )
Change subject: soc/intel/elkhartlake: Select SOC_INTEL_COMMON_BASECODE
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83944?usp=email )
Change subject: mb/google/nissa/var/riven: Set PCIE WLAN bluetooth companion device
......................................................................
mb/google/nissa/var/riven: Set PCIE WLAN bluetooth companion device
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345596420
TEST=Build and test on revin, check BRDS is shown in SSDT.
Change-Id: I87cfbdd0b8a97d84a96af373855219c60f39f173
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83944
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: V Sowmya <v.sowmya(a)intel.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
---
M src/mainboard/google/brya/variants/riven/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Dinesh Gehlot: Looks good to me, approved
V Sowmya: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 701277d..0481848 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -480,6 +480,7 @@
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_03"
register "add_acpi_dma_property" = "true"
+ use usb2_port10 as bluetooth_companion
device pci 00.0 on
probe WIFI_TYPE WIFI_PCIE
end
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83943?usp=email )
Change subject: mb/google/nissa/var/nivviks: Set PCIE WLAN bluetooth companion device
......................................................................
mb/google/nissa/var/nivviks: Set PCIE WLAN bluetooth companion device
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345596420
TEST=Build and test on nivviks, check BRDS is shown in SSDT.
Change-Id: Ib654f22033c68edbc602f14537aaa2151800598d
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83943
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: V Sowmya <v.sowmya(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/nivviks/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
V Sowmya: Looks good to me, approved
build bot (Jenkins): Verified
Dinesh Gehlot: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index bb56749..bf774e2 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -515,6 +515,7 @@
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_03"
register "add_acpi_dma_property" = "true"
+ use usb2_port10 as bluetooth_companion
device pci 00.0 on
probe WIFI_CATEGORY WIFI_7
end
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Subrata Banik has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/83986?usp=email )
Change subject: mb/google/nissa/var/riven: Set VccIn Aux Imon IccMax to 25A
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/brya/variants/riven/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83986/comment/95feeaee_20515590?us… :
PS1, Line 4:
u need to include console.h here
https://review.coreboot.org/c/coreboot/+/83986/comment/231618af_33bb3fb6?us… :
PS1, Line 7: // 25 * 4
nit
```
/* 25 * 4 */
```
please also elaborate what is 25 and 4 refers at ?
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Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83975?usp=email )
Change subject: soc/intel/alderlake: Refactor eSOL for late CSE sync text message
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83975/comment/d7d1cd24_1abba5e4?us… :
PS1, Line 479: CONFIG(MAINBOARD_HAS_EARLY_LIBGFXINIT))
> I would suggest using `MAINBOARD_HAS_EARLY_LIBGFXINIT` because the latest unified eSoL config is not known to the earlier firmware like ADL-N.
I guess @jayvik@google.com tries to convey to align the implementation same as MTL https://review.coreboot.org/c/coreboot/+/83769/27/src/soc/intel/meteorlake/… where SoC shouldn't be aware what is the underlying technology being used for eSOL (libgfxinit or uGOP).
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Change subject: soc/intel/alderlake: Refactor eSOL for late CSE sync text message
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83975/comment/7b8f660f_750b8dc2?us… :
PS1, Line 479: CONFIG(MAINBOARD_HAS_EARLY_LIBGFXINIT))
> maybe we can use the recently implemented unified eSOL config for this ? ```CHROMEOS_ENABLE_ESOL```
I would suggest using `MAINBOARD_HAS_EARLY_LIBGFXINIT` because the latest unified eSoL config is not known to the earlier firmware like ADL-N.
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