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Change subject: soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
......................................................................
soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
These field defines are SOC-specific. The AUX bias virtual wire field
positons are shifted in PTL.
In MTL SOC and older:
7:0 GROUP_ID Group ID in PCH GPIO
10:8 BIT_NUM Data bit Position in PCH GPIO
23:16 VW_INDEX VW Index in PCH GPIO
In PTL SOC:
15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 BIT_NUM Data bit Position in PCH GPIO
31:24 VW_INDEX VW Index in PCH GPIO
BUG=361048817
TEST=boot to OS and use iotools to read AUX Bias Ctrl register to
verify the group ID, bit number, and vw index.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996
---
M src/soc/intel/alderlake/include/soc/tcss.h
M src/soc/intel/common/block/tcss/tcss.c
M src/soc/intel/meteorlake/include/soc/tcss.h
M src/soc/intel/tigerlake/include/soc/tcss.h
4 files changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/83980/4
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and fix vw mapping
......................................................................
Patch Set 5:
(2 comments)
File src/soc/intel/common/block/gpio/Kconfig:
https://review.coreboot.org/c/coreboot/+/83981/comment/f3b4d903_dbad38a6?us… :
PS5, Line 66: config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID
: bool
: default n
: help
: In newer SOC, port ID has been extended to 16-bit. This must be set to accommodate
: the structure to hold the 16-bit value.
:
```
config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID
bool
default n
help
Enable support for 16-bit CPU Port IDs.
Intel SoCs (starting with Panther Lake) have extended the CPU Port ID
field to 16 bits.
Enable this option if your platform requires the GPIO driver to
accommodate this larger Port ID value.
```
File src/soc/intel/common/block/include/intelblocks/gpio.h:
https://review.coreboot.org/c/coreboot/+/83981/comment/bd4adcdc_52b8d16b?us… :
PS5, Line 113: /* virtual-wire mapping base and the starting bit position for a group */
: struct vw_map {
: uint8_t base;
: uint8_t start_pos;
: };
keep this part of the vw cl
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and fix vw mapping
......................................................................
Patch Set 5:
(4 comments)
Patchset:
PS5:
can you split this cl into two cls
1. 16-bit cpu port (kconfig and .h)
2. vm index changes as PTL vm entries are not continuous
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/83981/comment/c09656b6_7c57cc3a?us… :
PS5, Line 1062: /* Get the community (potentially updating 'comm' if vw_map exists) */
: comm = gpio_get_community(pad);
remove this as line #1060
https://review.coreboot.org/c/coreboot/+/83981/comment/4ada9755_8bf7b737?us… :
PS5, Line 1064:
: /* Find the VW entry containing 'pad' */
same as well
https://review.coreboot.org/c/coreboot/+/83981/comment/bce81235_bcf0ce47?us… :
PS5, Line 1073: /* Check if we found a valid entry */
u can drop this comment. I have added that for explanation 😎
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Change subject: soc/intel/common/block/cpu: Round up the number of ways
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and fix vw mapping
......................................................................
Patch Set 4:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83981/comment/fe1ca491_8c40243b?us… :
PS4, Line 7: and vw mapping fix
> Please make this a statement: […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83981/comment/693bbe26_5a180fd6?us… :
PS4, Line 9: Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
: Change cpu_port field to 16-bit width if the Kconfig is set.
> Please do not break lines, just because a new sentence starts. Or format it as a list.
Acknowledged
https://review.coreboot.org/c/coreboot/+/83981/comment/2d827560_bb060e17?us… :
PS4, Line 13: vw_index and position are not continuous in between groups within a
: community.
> can you please point me the EDS section for understand this claim ?
I don't see these vw_index and bit position in EDS. I can provide a brief info here to help understand the existing code for vw_index and position calculation and the purpose of this CL change:
VW index bit position
com0:
GPP_C_00: 10h 0 <- base is 0x10 for the community
...
GPP_C_07: 10h 7
GPP_C_08: 11h 0
...
GPP_C_23: 12h 7
com1:
GPP_F_00: 10h 0 <- base is 0x10 for the community
...
GPP_F_23: 12h 7
GPP_E_00: 13h 0
...
GPP_E_22: 15h 6
com3:
GPP_A_00: 10h 0 <- base is 0x10 for the community
...
GPP_A_17: 12h 1
GPP_H_00: 13h 0 <- previous positon is 1, but start from 0
...
GPP_H_24: 16h 0
com5:
GPP_B_00: 10h 3 <- bit position not 0
...
GPP_B_25: 13h 1
GPP_D_00: 14h 0 <- previous position is 1, skip to start from 0
...
GPP_D_25: 17h 1
File src/soc/intel/common/block/gpio/Kconfig:
https://review.coreboot.org/c/coreboot/+/83981/comment/d186e23d_9aeac43d?us… :
PS4, Line 70: Use 16-bit CPU port ID.
> please use some elaborated help text for folks to understand when to select this Kconfig.
Acknowledged
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/83981/comment/9b437b37_c80b5ae5?us… :
PS4, Line 1064: comm = gpio_get_community(pad);
> oh. I thought I removed it. […]
Switched to your suggested code. Acknowledged
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Attention is currently required from: Bora Guvendik, Jamie Ryu, Jérémy Compostella, Saurabh Mishra, Subrata Banik, Wonkyu Kim.
Hello Bora Guvendik, Jamie Ryu, Jérémy Compostella, Saurabh Mishra, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and fix vw mapping
......................................................................
soc/intel/common/gpio: support 16-bit CPU Port ID and fix vw mapping
- Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
- Change cpu_port field to 16-bit width if the Kconfig is set.
- Add specific virtual wire mapping structure for:
1. First pad group does not starts with bit position 0.
2. vw_index and position are not continuous in between groups within a
community.
BUG=
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
---
M src/soc/intel/common/block/gpio/Kconfig
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
3 files changed, 37 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83981/5
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Change subject: soc/intel/common/block/cpu: Round up the number of ways
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/83982/comment/77870105_6e11f325?us… :
PS5, Line 515: Add one way if there is remainder
> the statement should be […]
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83982?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/cpu: Round up the number of ways
......................................................................
soc/intel/common/block/cpu: Round up the number of ways
`CONFIG_DCACHE_RAM_SIZE' is not necessarily a multiple of way size. As
a result, when the `div' instruction is called to compute the needed
number of ways, there could be a remainder. When there is, one extra
way should be added to cover `CONFIG_DCACHE_RAM_SIZE'.
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521e
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/83982/6
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