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Change subject: mb/lenovo/thinkcentre_m710s: Add SMBIOS data for PCIe slots
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Patch Set 1: Code-Review+2
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Change subject: mb/lenovo/thinkcentre_m710s: Disable DRIVER_LENOVO_SERIALS
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Change subject: mb/lenovo/thinkcentre_m710s: Drop PCH UPDs from PEG device
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Patch Set 1: Code-Review+2
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Change subject: mb/lenovo/thinkcentre_m710s: Add USB port descriptions
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Patch Set 1: Code-Review+2
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Change subject: mb/asrock: Add Asrock Industrial IMB-1222 motherboard
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Patch Set 16:
(5 comments)
File src/mainboard/asrock/imb-1222/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/83107/comment/68a7cb75_92b1cd8f?us… :
PS16, Line 6: .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
This is the default. Please remove.
https://review.coreboot.org/c/coreboot/+/83107/comment/e2ea0a8b_87dd154a?us… :
PS16, Line 45: device cpu_cluster 0 on end
Already in chipset devicetree. Please remove.
https://review.coreboot.org/c/coreboot/+/83107/comment/a519c43d_dcc0dffe?us… :
PS16, Line 91: device ref heci1 on end
Same as in chipset devicetree, please remove.
https://review.coreboot.org/c/coreboot/+/83107/comment/5ff510e1_c0ea3988?us… :
PS16, Line 143: device ref fast_spi on end
Same as in chipset devicetree, please remove.
File src/mainboard/asrock/imb-1222/fmap.fmd:
PS16:
Is there a reason for the custom fmap? It looks pretty much like a standard one.
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Change subject: soc/intel/common/gpio: vm index changes as PTL vm entries are not continuous
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Patch Set 1: Code-Review-2
(1 comment)
Patchset:
PS1:
blocking the code review due to https://review.coreboot.org/c/coreboot/+/83981/comments/74cb3b78_ddfadfc2
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
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Patch Set 7: Code-Review-2
(2 comments)
Patchset:
PS7:
I would like to block this code review for lack of documentation. I was hoping to get the documentation later and then land this code. However, I don't think the documentation will ever be available (https://review.coreboot.org/c/coreboot/+/83981/comment/fc8b310d_8450ae4d/).
Therefore, I am going to block this code review unless we have a way to understand the register details. I am not asking for the document to be made public, but it should be updated on Intel's portal (access control) so that anyone with access can review the code.
Commit Message:
https://review.coreboot.org/c/coreboot/+/83981/comment/5a58426a_d86304d4?us… :
PS4, Line 13: vw_index and position are not continuous in between groups within a
: community.
> I've asked this morning. waiting for response. I will try my best, but this might not have outcome.
Unable to follow what you mean by not having outcome. I believe MTL EDS had details about VW. If you are unable to get the required details then I'm going to block this CL review.
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