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Change subject: mb/asrock: Add Asrock Industrial IMB-1222 motherboard
......................................................................
Patch Set 16:
(1 comment)
Patchset:
PS16:
Please remove "duplicated" includes and include only what you use.
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Change subject: mb/acer/g43t-am3: Add Acer Q45T-AM as a variant
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/acer/g43t-am3/variants/q45t-am/early_init.c:
https://review.coreboot.org/c/coreboot/+/83968/comment/98d86947_b0d50d1c?us… :
PS3, Line 7: <superio/ite/it8720f/it8720f.h>
> Acknowledged. Will be done in a follow-up.
please keep me in Cc
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Change subject: mb/acer/g43t-am3: Remove duplicated files
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Patch Set 1: Code-Review+2
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Change subject: arch/x86: Move oformat definition into the linker file
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83999/comment/b7be4605_1e600371?us… :
PS2, Line 9: This removes the boilerplate --oformat out of the makefile.inc
Makefile.mk
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> Subrata,
> Here is the response from our EDS owner:
>
> Aux Biasing isolation control is only required for USB3 + DP retimer-less topology. The USB3 + DP configuration is not POR for PTL segment
Looks like you are bringing one more requirement here. In future there might be OxM designs with and without Retimer chip (Retimer is POR for CrOS for sure but that doesn't mean other can't have design w/o Retimer, for example: chromebase doesn't have retimer). Now to meet both such design req and SoC guidelines, you need to introduce a newer kconfig `SOC_INTEL_COMMON_TCSS_SKIP_AUX_PAD` (something meaningful). This stays enable by default and only set to `n` depending on the main board design assumes PTL, fatcat would override it to `N.
Inside aux programming in TCSS file, you should check if SOC_INTEL_COMMON_TCSS_SKIP_AUX_PAD is set then skip the programming.
>
> If agree, we can just let .configure_aux_bias_pads unconfigured in PTL tcss.c and remove all the virtual wire mapping in PTL gpio.c. Please let me know.
This doesn't have any relation if we wish to update the EDS or not. EDS has to be updated irrespective if CrOS is using or not. this is SOC req.
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Change subject: mb/lenovo/thinkcentre_m710s: Disable DRIVER_LENOVO_SERIALS
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I think the Kconfig could use a bit of cleaning but it's out of scope for this patch
How so? I would be happy to do some cleaning. 😊
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Change subject: mb/google/nissa/var/riven: Set VccIn Aux Imon IccMax to 25A
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/brya/variants/riven/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83986/comment/de183f64_8b654716?us… :
PS1, Line 4:
> u need to include console. […]
Done
https://review.coreboot.org/c/coreboot/+/83986/comment/77948bcb_d739877c?us… :
PS1, Line 7: // 25 * 4
> nit […]
Done
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Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Simon Yang, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/var/riven: Set VccIn Aux Imon IccMax to 25A
......................................................................
mb/google/nissa/var/riven: Set VccIn Aux Imon IccMax to 25A
Iccmax of VccIn_Aux is 25A with MBVR design.
BUG=b:348258637
TEST=Local build successfully and boot to OS normally.
Change-Id: I59c420c03a8f01d185f616a2212798266b4251e0
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/riven/Makefile.mk
A src/mainboard/google/brya/variants/riven/ramstage.c
2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/83986/2
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Change subject: soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
......................................................................
soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
These field defines are SOC-specific. The AUX bias virtual wire field
positons are shifted in PTL.
In MTL SOC and older:
7:0 GROUP_ID Group ID in PCH GPIO
10:8 BIT_NUM Data bit Position in PCH GPIO
23:16 VW_INDEX VW Index in PCH GPIO
In PTL SOC:
15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 BIT_NUM Data bit Position in PCH GPIO
31:24 VW_INDEX VW Index in PCH GPIO
BUG=361048817
TEST=boot to OS and use iotools to read AUX Bias Ctrl register to
verify the group ID, bit number, and vw index.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996
---
M src/soc/intel/alderlake/include/soc/tcss.h
M src/soc/intel/common/block/tcss/tcss.c
M src/soc/intel/meteorlake/include/soc/tcss.h
M src/soc/intel/tigerlake/include/soc/tcss.h
4 files changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/83980/5
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