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Change subject: mb/google/brox: Enable storage devices on unprovisioned fw_config
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> > That needs provisioning the FW_CONFIG with value 0 or whatever is equivalent to STORAGE_UNKNOWN. […]
Ack. This change is targeted towards factory and hence it should not impact the already shipped devices if rolled out.
But to avoid any disruption, we can keep this change in a firmware looking manner.
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Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Wonkyu Kim.
Hello Bora Guvendik, Jamie Ryu, Jérémy Compostella, Saurabh Mishra, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................
soc/intel/common/gpio: support 16-bit CPU Port ID
- Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
- Change cpu_port field to 16-bit width if the Kconfig is set.
BUG=
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
---
M src/soc/intel/common/block/gpio/Kconfig
M src/soc/intel/common/block/include/intelblocks/gpio.h
2 files changed, 15 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83981/7
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................
Patch Set 6:
(2 comments)
File src/soc/intel/common/block/include/intelblocks/gpio.h:
https://review.coreboot.org/c/coreboot/+/83981/comment/2a43691c_dd4ed1db?us… :
PS6, Line 161: const struct vw_map *vw_map;
same
File src/soc/intel/common/block/include/intelblocks/gpio.h:
https://review.coreboot.org/c/coreboot/+/83981/comment/902bc0e9_c4b630be?us… :
PS5, Line 113: /* virtual-wire mapping base and the starting bit position for a group */
: struct vw_map {
: uint8_t base;
: uint8_t start_pos;
: };
> will do
move this into other virtual wire cl?
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Change subject: mb/google/brox: Enable storage devices on unprovisioned fw_config
......................................................................
Patch Set 2: Code-Review+1
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................
soc/intel/common/gpio: support 16-bit CPU Port ID
- Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
- Change cpu_port field to 16-bit width if the Kconfig is set.
BUG=
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
---
M src/soc/intel/common/block/gpio/Kconfig
M src/soc/intel/common/block/include/intelblocks/gpio.h
2 files changed, 22 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83981/6
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and fix vw mapping
......................................................................
Patch Set 5:
(6 comments)
Patchset:
PS5:
> can you split this cl into two cls […]
sure. this sounds better. will do.
File src/soc/intel/common/block/gpio/Kconfig:
https://review.coreboot.org/c/coreboot/+/83981/comment/5edf53dc_e71e3b1c?us… :
PS5, Line 66: config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID
: bool
: default n
: help
: In newer SOC, port ID has been extended to 16-bit. This must be set to accommodate
: the structure to hold the 16-bit value.
:
> ``` […]
Thx for helping out!
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/83981/comment/e0461ed6_b81fc1f3?us… :
PS5, Line 1062: /* Get the community (potentially updating 'comm' if vw_map exists) */
: comm = gpio_get_community(pad);
> remove this as line #1060
my bad again. Acknowledged
https://review.coreboot.org/c/coreboot/+/83981/comment/37403f31_e01f4917?us… :
PS5, Line 1064:
: /* Find the VW entry containing 'pad' */
> same as well
Acknowledged
https://review.coreboot.org/c/coreboot/+/83981/comment/d35d2df9_0c22443d?us… :
PS5, Line 1073: /* Check if we found a valid entry */
> u can drop this comment. […]
Acknowledged
File src/soc/intel/common/block/include/intelblocks/gpio.h:
https://review.coreboot.org/c/coreboot/+/83981/comment/c1352eb0_9c2f52ae?us… :
PS5, Line 113: /* virtual-wire mapping base and the starting bit position for a group */
: struct vw_map {
: uint8_t base;
: uint8_t start_pos;
: };
> keep this part of the vw cl
will do
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Change subject: mb/google/brox: Enable storage devices on unprovisioned fw_config
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> That needs provisioning the FW_CONFIG with value 0 or whatever is equivalent to STORAGE_UNKNOWN. As more devices are built during the later hardware build phases, this is going to be hard to provision the FW_CONFIG with that special value. Also that takes away a field option unnecessarily.
>
> With this change, the plan is to get rid of STORAGE_UNKNOWN.
I think this is a good plan, especially since we're currently working on Intel RVP. My only concern is that all devices are running from the FW branch, and I hope they don't need to adhere to this new change. Going forward, we should use this new norm for all CrOS devices.
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