David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83331?usp=email )
Change subject: lib/smbios: Create SMBIOS type 4 entry
......................................................................
lib/smbios: Create SMBIOS type 4 entry
One smbios type 4 should be provided for each CPU instance.
Create SMBIOS type 4 entry according to socket number, with a
default value of 1.
TEST=Boot on intel/archercity CRB
No changes in boot log and 'dmidecode' result under centos
Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83331
Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/include/smbios.h
M src/lib/Kconfig
M src/lib/smbios.c
M src/soc/intel/xeon_sp/util.c
4 files changed, 24 insertions(+), 3 deletions(-)
Approvals:
Lean Sheng Tan: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/include/smbios.h b/src/include/smbios.h
index 8ef37d8..b5b9e7a 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -74,6 +74,8 @@
unsigned int smbios_cpu_get_max_speed_mhz(void);
unsigned int smbios_cpu_get_current_speed_mhz(void);
unsigned int smbios_cpu_get_voltage(void);
+unsigned int smbios_get_max_sockets(void);
+unsigned int smbios_soc_get_max_sockets(void);
const char *smbios_mainboard_manufacturer(void);
const char *smbios_mainboard_product_name(void);
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index e896704..2c1a93c 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -49,6 +49,10 @@
It is multiplication of number of channel to number of DIMMs per
channel
+config MAX_SOCKET
+ int
+ default 1
+
config DIMM_SPD_SIZE
int
default 256
diff --git a/src/lib/smbios.c b/src/lib/smbios.c
index ca71e3b..58caf8c 100644
--- a/src/lib/smbios.c
+++ b/src/lib/smbios.c
@@ -443,6 +443,14 @@
return 0; /* Unknown */
}
+unsigned int smbios_get_max_sockets(void)
+{
+ if (CONFIG_MAX_SOCKET == 1)
+ return 1;
+ else
+ return smbios_soc_get_max_sockets();
+}
+
static int smbios_write_type1(unsigned long *current, int handle)
{
struct smbios_type1 *t = smbios_carve_table(*current, SMBIOS_SYSTEM_INFORMATION,
@@ -1233,9 +1241,11 @@
handle++;
update_max(len, max_struct_size, smbios_write_type3(¤t, handle++));
- struct smbios_type4 *type4 = (struct smbios_type4 *)current;
- update_max(len, max_struct_size, smbios_write_type4(¤t, handle++));
- len += smbios_write_type7_cache_parameters(¤t, &handle, &max_struct_size, type4);
+ for (unsigned int s = 0; s < smbios_get_max_sockets(); s++) {
+ struct smbios_type4 *type4 = (struct smbios_type4 *)current;
+ update_max(len, max_struct_size, smbios_write_type4(¤t, handle++));
+ len += smbios_write_type7_cache_parameters(¤t, &handle, &max_struct_size, type4);
+ }
update_max(len, max_struct_size, smbios_write_type11(¤t, &handle));
if (CONFIG(ELOG))
update_max(len, max_struct_size,
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index 4dbe7a4..bf07ee7 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -90,6 +90,11 @@
return get_iio_uds()->SystemStatus.numCpus;
}
+unsigned int smbios_soc_get_max_sockets(void)
+{
+ return soc_get_num_cpus();
+}
+
union p2sb_bdf soc_get_hpet_bdf(void)
{
if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) {
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Change subject: mb/google/dedede/var/galtic: Add fw_config option for touchpad type
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Sorry, I meant querying what the device is over i2c.
we'd probably want that as an optional 2nd step beyond just presence detection, but IMO this is exactly the problem SSFC exists to solve, so I'm not sure why it wasn't used here from the start
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Change subject: arch/x86/Kconfig: Stop building ARM verstage with clang
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83594/comment/9b60f81f_636709e2?us… :
PS1, Line 9: We have never intended to build ARM verstage with clang (see CB:69701).
> > The moment we try to pull in CMOS related support into ARM/PSP verstage (CB:83495), we are running […]
@yupingso@google.com, Can you please try -Oz compiler optimization flag here - https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/he…
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Angel Pons has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/libgfxinit/+/83599?usp=email )
Change subject: gma: Re-structure TC port types
......................................................................
Patch Set 1:
(1 comment)
File common/hw-gfx-gma-config_helpers.adb:
https://review.coreboot.org/c/libgfxinit/+/83599/comment/b2ae62bf_22312eac?… :
PS1, Line 68:
: when DP_TC1 | HDMI_TC1 | USBC1 => DDI_TC3,
: when DP_TC2 | HDMI_TC2 | USBC2 => DDI_TC4,
: when DP_TC3 | HDMI_TC3 | USBC3 => DDI_TC5,
: when DP_TC4 | HDMI_TC4 | USBC4 => DDI_TC6,
> Might be a brainfart anyway. They use ports F..I in the ADL VBT instead […]
ADL-P (XeLPD) doesn't even have TC5 .. TC6 so it definitely feels wrong. Also, I remember the ADL patches from Chrome folks only map registers for TC1 .. TC4 on ADL.
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Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83346?usp=email )
Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
If user continues to use the touchpad for over 3 minutes on Xol, the
pointer movement is stuttering.
Touchpad I2C transaction should appear during the interrupt signal level
is low, but we could see some more I2C transaction after the interrupt
signal(GPP_F14) went to high.
We found experimentally that changing the interrupt type to GPIO_INT
from APIC_IRQ improved this issue. We are still investigating, would
like to apply this change first for Xol's dogfooding.
BUG=b:350609957
BRANCH=brya
TEST=built and verified there's no stuttering issue on touchpad movement
Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83346
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: YH Lin <yueherngl(a)google.com>
---
M src/mainboard/google/brya/variants/xol/gpio.c
M src/mainboard/google/brya/variants/xol/overridetree.cb
2 files changed, 12 insertions(+), 2 deletions(-)
Approvals:
YH Lin: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c
index 39478a1..9e49784 100644
--- a/src/mainboard/google/brya/variants/xol/gpio.c
+++ b/src/mainboard/google/brya/variants/xol/gpio.c
@@ -119,6 +119,13 @@
PAD_NC(GPP_F12, NONE),
/* F13 : GSXDOUT ==> NC */
PAD_NC(GPP_F13, NONE),
+ /* F14 : GSXDIN ==> TCHPAD_INT_ODL */
+ /*
+ * FIXME: Change back the interrupt type to IRQxAPIC if possible after investigating
+ * the reason why Xol shows touchpad stuttering issue with IRQxAPIC
+ * configuration but not GPI_INT.
+ */
+ PAD_CFG_GPI_INT(GPP_F14, NONE, PWROK, LEVEL),
/* F15 : GSXSRESET# ==> PU 100K 3.3V */
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
/* F16 : GSXCLK ==> NC */
diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb
index d73702c..5de8c73 100644
--- a/src/mainboard/google/brya/variants/xol/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xol/overridetree.cb
@@ -343,8 +343,11 @@
chip drivers/i2c/hid
register "generic.hid" = ""ZNT0000""
register "generic.desc" = ""Zinitix Touchpad""
- register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
- register "generic.wake" = "GPE0_DW2_14"
+ # FIXME: Change back the interrupt type to IRQxAPIC if possible
+ # after investigating the reason why Xol shows touchpad
+ # stuttering issue with IRQxAPIC configuration but not
+ # GPI_INT.
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_F14)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0xE"
device i2c 40 on end
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Change subject: mb/google/dedede/var/galtic: Add fw_config option for touchpad type
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Have a good way to distinguish between the two touchpads on the same i2c address? Right now both are […]
Sorry, I meant querying what the device is over i2c.
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Nico Huber has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/libgfxinit/+/83599?usp=email )
Change subject: gma: Re-structure TC port types
......................................................................
Patch Set 1:
(1 comment)
File common/hw-gfx-gma-config_helpers.adb:
https://review.coreboot.org/c/libgfxinit/+/83599/comment/7ef1b073_7b4c28fd?… :
PS1, Line 68:
: when DP_TC1 | HDMI_TC1 | USBC1 => DDI_TC3,
: when DP_TC2 | HDMI_TC2 | USBC2 => DDI_TC4,
: when DP_TC3 | HDMI_TC3 | USBC3 => DDI_TC5,
: when DP_TC4 | HDMI_TC4 | USBC4 => DDI_TC6,
> Not entirely sure about this, I'd like to revise
Might be a brainfart anyway. They use ports F..I in the ADL VBT instead
of D..G (TGL). However if I understand Linux correctly now, it maps this
to TC1..4 too (`display/intel_bios.c`).
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Change subject: arch/x86/Kconfig: Stop building ARM verstage with clang
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83594/comment/dbf2de62_013ebb5e?us… :
PS1, Line 9: We have never intended to build ARM verstage with clang (see CB:69701).
> The moment we try to pull in CMOS related support into ARM/PSP verstage (CB:83495), we are running out of space in PSP SRAM i.e. text, data and bss sections together are going beyond their allocated range in psp_verstage memlayout. This is happening only with clang. GCC builds fine.
I see. I don't think removing clang support for most AMD platforms is the right approach here. I'm working on LTO which should reduce the size. In the mean time I noticed that using -Oz instead of -Os with clang reduces the verstage of a few Kb which should solve your issues. I suggest adding the CFLAG for just the ARM verstage for AMD in combination with clang as a temporary workaround.
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Change subject: mb/google/dedede/var/galtic: Add fw_config option for touchpad type
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Any idea what the boot time difference would be on just detecting this instead so we don't need to q […]
Have a good way to distinguish between the two touchpads on the same i2c address? Right now both are "detected" bc all we do is check if there is a device present at the address
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Jon Murphy has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/83606?usp=email )
Change subject: mb/google/dedede/var/galtic: Add fw_config option for touchpad type
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Patch Set 1:
(1 comment)
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PS1:
Any idea what the boot time difference would be on just detecting this instead so we don't need to query fw config?
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