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Change subject: commonlib: cbmem_id: Add id for ACPI BDAT
......................................................................
Patch Set 13: Code-Review+1
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Change subject: mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/intel/beechnutcity_crb/Kconfig:
https://review.coreboot.org/c/coreboot/+/83327/comment/d102cdb6_ff059567?us… :
PS3, Line 21: config CARDBUS_PLUGIN_SUPPORT
> Redundant with the above config option. […]
Good catch, there is duplication, I removed it. We are not doing cardbus support in BHS, the Kconfig is just to disable the setting (otherwise it will be by default enabled).
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Change subject: mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info
......................................................................
mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info
Update BIOS version and unset card bus plugin support.
Update wake-up type and SKU number.
Update mainboard asset tag and feature flags.
Update mainboard enclosure type, chassis version, chassis serial
number and chassis power cords.
Change-Id: I8a7d4958171df121e2cd3acb3a71554c695d64ab
Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com>
---
M src/mainboard/intel/beechnutcity_crb/ramstage.c
1 file changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/83327/4
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Change subject: soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/xeon_sp/romstage.c:
https://review.coreboot.org/c/coreboot/+/83325/comment/09312253_d3d1b474?us… :
PS3, Line 43: #if CONFIG(SOC_INTEL_SKYLAKE_SP)
> It is because SKX doesn't support the HOB context needed to obtain the DIMM info, but the SKX will s […]
I suppose I got your points, done :)
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Change subject: soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
......................................................................
soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
TEST=Build and boot on archercity CRB
No changes in boot log and 'dmidecode' result under centos
TEST=Build and boot on avenuecity CRB
It will add DMI type 16,17,19,20
Change-Id: I2f5b7a4ffabed033d54d4724b3c41246503166fe
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/cpx/Makefile.mk
M src/soc/intel/xeon_sp/cpx/romstage.c
A src/soc/intel/xeon_sp/dimm.c
M src/soc/intel/xeon_sp/gnr/Makefile.mk
M src/soc/intel/xeon_sp/gnr/romstage.c
M src/soc/intel/xeon_sp/include/soc/romstage.h
M src/soc/intel/xeon_sp/romstage.c
M src/soc/intel/xeon_sp/skx/romstage.c
M src/soc/intel/xeon_sp/spr/Makefile.mk
M src/soc/intel/xeon_sp/spr/romstage.c
10 files changed, 162 insertions(+), 169 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83325/6
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Change subject: soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
......................................................................
Patch Set 5:
(4 comments)
File src/soc/intel/xeon_sp/gnr/romstage.c:
https://review.coreboot.org/c/coreboot/+/83325/comment/778a840f_79bfd8d1?us… :
PS3, Line 90: uint8_t get_dram_type(void)
: {
: const struct SystemMemoryMapHob *hob = get_system_memory_map();
: if (hob && hob->DramType == SPD_MEMORY_TYPE_DDR5_SDRAM)
> The code that has been factored out (made shared) uses `struct SystemMemoryMapHob` already. […]
Done
File src/soc/intel/xeon_sp/romstage.c:
https://review.coreboot.org/c/coreboot/+/83325/comment/adde63e1_85d86e62?us… :
PS3, Line 43: #if CONFIG(SOC_INTEL_SKYLAKE_SP)
> Hmmm, instead of this, why not place `save_dimm_info()` in a separate `dimm_info. […]
It is because SKX doesn't support the HOB context needed to obtain the DIMM info, but the SKX will still get save_dimm_info() called from the common codes (mainboard_romstage_entry). Since the common code will always call save_dimm_info for SKX, it looks like putting save_dimm_info() to a separate file still not mitigate this issue. Or let us define save_dimm_info() as __weak and override to a null implementation for SKX?
https://review.coreboot.org/c/coreboot/+/83325/comment/399c9fd0_4ceaee3a?us… :
PS3, Line 69:
: for (int skt = 0; skt < CONFIG_MAX_SOCKET; skt++) {
: for (int ch = 0; ch < MAX_CH; ch++) {
: for (int dimm = 0; dimm < get_max_dimm_count(); dimm++) {
> nit: if `get_max_dimm_count()` always returns the same value, I would add a helper constant: […]
Done
File src/soc/intel/xeon_sp/spr/romstage.c:
https://review.coreboot.org/c/coreboot/+/83325/comment/83b7ed7d_a5c63b85?us… :
PS3, Line 132: uint32_t get_max_capacity_mib(void)
> Move this next to the other functions?
Done
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Hello Yan-tingX Chen,
I'd like you to do a code review.
Please visit
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Change subject: soc/intel/xeon_sp/Kconfig: Disable ANSI escape code
......................................................................
soc/intel/xeon_sp/Kconfig: Disable ANSI escape code
To remove ANSI escape sequences (like `ESC [1m`) from boot log.
Change-Id: I7473b55d536d3bdfee151e31ecbc52f703b99b17
Signed-off-by: Chen Yan TingX <yan-tingx.chen(a)intel.com>
---
M src/soc/intel/xeon_sp/Kconfig
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/83610/1
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 22cc366..3a7e76d 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -110,4 +110,8 @@
config SOC_INTEL_HAS_CXL
bool
+config CONSOLE_USE_ANSI_ESCAPES
+ bool "Use ANSI escape sequences for console highlighting"
+ default n
+
endif ## SOC_INTEL_XEON_SP
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Change subject: soc/intel/xeon_sp: Reserve FSP MMIO high window
......................................................................
soc/intel/xeon_sp: Reserve FSP MMIO high window
Xeon-SP supports MMIO high window, a.k.a. MMIO window above 4G.
FSP will assign MMIO high ranges to domains as domain MMIO high
windows. However, there will be unassigned parts among domain
windows for non-domain usage, which will cause segmentation in
MTRR UC coverage.
Reserve MMIO high as a whole under domain0/00:0.0. During MTRR
calculation, this MMIO high reservation will connect the
discontinued domain high MMIO windows together to form one
continuous range and to save MTRR usage from inadequacy.
Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/uncore.c
6 files changed, 50 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/83538/2
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Change subject: util/autoport/*.md: List Haswell as supported
......................................................................
Patch Set 2: Code-Review+2
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Gerrit-Comment-Date: Tue, 23 Jul 2024 02:31:16 +0000
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