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Change subject: arch/x86/Kconfig: Move AMD stages arch to common code
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> > Okay. […]
Acknowledged
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Change subject: soc/amd/psp_verstage: Add -Oz flag for clang
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83594/comment/7b971ee2_99415d57?us… :
PS1, Line 9: We have never intended to build ARM verstage with clang (see CB:69701).
> @yupingso@google.com, Can you please try -Oz compiler optimization flag here - https://chromium. […]
The `-Oz` flag can solve the build issue. Guybrush has 148K `PSP_SRAM_SIZE` and 40K `PSP_VERSTAGE_STACK_SIZE`, leaving 108K for verstage plus the transfer buffer. The transfer buffer takes about 27K, so verstage must be less than 81K.
Some statistics of verstage size (from `_everstage - _verstage` in GOOGLE_GUYBRUSH/cbfs/fallback/verstage.map):
- gcc: 67K
- clang without `-Oz`: 81K
- clang with `-Oz`: 76K
Re-purposed this patch to add the `-Oz` flag as suggested.
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Hello Arthur Heymans, Jérémy Compostella, Karthik Ramasubramanian, Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/amd/psp_verstage: Add -Oz flag for clang
......................................................................
soc/amd/psp_verstage: Add -Oz flag for clang
When we tried to add CMOS support to PSP verstage (CB:83495), the clang
builds failed on boards with cezanne SoC (such as Guybrush), due to
over-sized verstage. On the other hand, there is no such problem for gcc
builds on the same boards.
Building PSP verstage by clang generates much larger verstage size (81K)
compared with using gcc (67K). To unblock adding features to verstage,
temporarily enable -Oz for clang builds.
Change-Id: I033458556986ade88fb8e68499b632deae4dd419
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/amd/common/psp_verstage/Makefile.mk
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/83594/2
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Change subject: drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
......................................................................
drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A
is bank selection. Since the MC146818 driver accesses VBNV via Bank 0,
the value set in cmos_init() must not contain that bit.
To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add
an static assertion about the bank selection for AMD. Note that the
kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/d…
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: I6122201914c40604f86dcca6025b55c595ef609e
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83537
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M src/drivers/pc80/rtc/mc146818rtc.c
M src/include/pc80/mc146818rtc.h
2 files changed, 5 insertions(+), 0 deletions(-)
Approvals:
Karthik Ramasubramanian: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c
index b4ddadd..1c4428a 100644
--- a/src/drivers/pc80/rtc/mc146818rtc.c
+++ b/src/drivers/pc80/rtc/mc146818rtc.c
@@ -65,6 +65,9 @@
#define RTC_CONTROL_DEFAULT (RTC_24H)
#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ)
+_Static_assert(!CONFIG(SOC_AMD_COMMON) || !(RTC_FREQ_SELECT_DEFAULT & RTC_AMD_BANK_SELECT),
+ "Bank 1 should not be selected for AMD");
+
static bool __cmos_init(bool invalid)
{
bool cmos_invalid;
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 7818421..701cc73 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -33,6 +33,8 @@
# define RTC_REF_CLCK_4MHZ 0x00
# define RTC_REF_CLCK_1MHZ 0x10
# define RTC_REF_CLCK_32KHZ 0x20
+ /* In AMD BKDG, bit 4 is DV0 bank selection. Bits 5 and 6 are reserved. */
+# define RTC_AMD_BANK_SELECT 0x10
/* 2 values for divider stage reset, others for "testing purposes only" */
# define RTC_DIV_RESET1 0x60
# define RTC_DIV_RESET2 0x70
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Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> I have made some changes to migrate some headers/APIs into common code to ease the PTL development. […]
Hi, sure will follow the tag "IA_COMMON_CODE"
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Change subject: soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
File src/soc/intel/xeon_sp/skx/romstage.c:
https://review.coreboot.org/c/coreboot/+/83325/comment/65c9017a_b8f57933?us… :
PS6, Line 28: void save_dimm_info(void) {}
Sure, this works. It's also quite obvious that it's not implemented for SKX.
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