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Change subject: mb/google/dedede/var/galtic: Add fw_config option for touchpad type
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/dedede/variants/galtic/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83606/comment/37849c52_b54ceac2?us… :
PS1, Line 12: TOUCHPAD_SOURCE 44 45
> As Martin pointed out, it has to be done through a provisioning process. […]
done: https://issuetracker.google.com/issues/354748059
will update this patch once the field has been provisioned
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Change subject: util/autoport/*.md: List Haswell as supported
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Technically `Documentation/util.md` and `util/README.md` should be updated as well since `util/autoport/description.md` was updated, but there are several other commits that those two markdown files are out of sync with. I'll regenerate them in a separate commit.
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Nicholas Chin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83609?usp=email )
Change subject: util/autoport/*.md: List Haswell as supported
......................................................................
util/autoport/*.md: List Haswell as supported
As of commit 3f0bb2fb0741 (autoport: Add support for Haswell-Lynx Point
platform), autoport supports Haswell in addition to Sandy Bridge and Ivy
Bridge.
Change-Id: Iccc10441389580ff8e89c3718484d25d20970f68
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
M util/autoport/description.md
M util/autoport/readme.md
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/83609/2
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Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83609?usp=email )
Change subject: autoport/*.md: List Haswell as supported
......................................................................
autoport/*.md: List Haswell as supported
As of commit 3f0bb2fb0741 (autoport: Add support for Haswell-Lynx Point
platform), autoport supports Haswell in addition to Sandy Bridge and Ivy
Bridge.
Change-Id: Iccc10441389580ff8e89c3718484d25d20970f68
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
M util/autoport/description.md
M util/autoport/readme.md
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/83609/1
diff --git a/util/autoport/description.md b/util/autoport/description.md
index 9a0e8d4..361a9f2 100644
--- a/util/autoport/description.md
+++ b/util/autoport/description.md
@@ -1 +1 @@
-Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go`
+Automated porting coreboot to Sandy Bridge/Ivy Bridge/Haswell platforms `Go`
diff --git a/util/autoport/readme.md b/util/autoport/readme.md
index 149e1ca..b755d43 100644
--- a/util/autoport/readme.md
+++ b/util/autoport/readme.md
@@ -3,8 +3,8 @@
## Supported platforms
### Chipset
-For any Sandy Bridge or Ivy Bridge platform the generated result should
-be bootable, possibly with minor fixes.
+For any Sandy Bridge, Ivy Bridge, or Haswell platform the generated result
+should be bootable, possibly with minor fixes.
### EC / SuperIO
EC support is likely to work on Intel-based thinkpads. Other laptops are
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Change subject: mb/google/dedede/var/awasuki: Initialise overridetree
......................................................................
Patch Set 8: Code-Review+2
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Change subject: soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibility
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83540/comment/279fe472_40ae3414?us… :
PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements
> > > > Why the 32KiB? this makes it sound like coreboot would need that much. […]
To clarify, there's no reason to make it 32 specifically, it just seems like a number that's big enough to make sure that even if we miss something or future changes add more, it should be way bigger than what we need (and as long as we don't run out of CAR space there's no reason not to make it bigger).
We've been investigating a bug that's probably caused by memory corruption in the VBOOT2_WORK area in CAR, and we think that stack overflow in the FSP may be a possible cause (because on the affected devices the CAR stack comes right after that region). We don't have any proof (it's a rare bug and tough to nail down) but 1KB is clearly way too low so it sounds like a good idea to bump this up either way.
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Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83607?usp=email )
Change subject: mb/asus/p8z77-m_pro/overridetree.cb: Correct PCIe devices config
......................................................................
mb/asus/p8z77-m_pro/overridetree.cb: Correct PCIe devices config
Match PCIe root port allocation and associated comments to
boardview, as follows:
Z77 PCIe ports 1-4: PCIEX16_3 (x4)
Z77 PCIe port 5: PCIEX1_1
Z77 PCIe port 6: RTL8111F LAN
Z77 PCIe port 7: ASM1042 USB3
Z77 PCIe port 8: ASM1061 eSATA
CPU PCIe lanes 1-8: PCIEX16_1
CPU PCIe lanes 9-16: Multiplexed via 4x ASM1480 to PCIEX16_1 lanes 9-16
and PCIEX16_2 lanes 1-8
(CPU PCIe lanes are not covered by overridetree.cb.)
These are not hardware tested.
Change-Id: I472e28add254ea945b401d1ddfd03f29f46d8fd2
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
1 file changed, 4 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83607/1
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
index 4613c12..0483f4a 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
@@ -25,13 +25,10 @@
}"
device ref pcie_rp1 on end # PCIEX_16_3
- device ref pcie_rp2 on end # RTL8111F
- device ref pcie_rp3 off end
- device ref pcie_rp4 off end
- device ref pcie_rp5 off end
- device ref pcie_rp6 on end # ASM1042 USB3
- device ref pcie_rp7 on end # ASM1061 eSATA
- device ref pcie_rp8 off end
+ device ref pcie_rp5 on end # PCIEX1_1
+ device ref pcie_rp6 on end # RTL8111F
+ device ref pcie_rp7 on end # ASM1042 USB3
+ device ref pcie_rp8 on end # ASM1061 eSATA
device ref lpc on
chip superio/nuvoton/nct6779d
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Change subject: mb/google/dedede/var/galtic: Add fw_config option for touchpad type
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/dedede/variants/galtic/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83606/comment/7f315775_d7ce55a6?us… :
PS1, Line 12: TOUCHPAD_SOURCE 44 45
> +1 on the upper bits. […]
As Martin pointed out, it has to be done through a provisioning process. Can you please file a bug request so that it can be routed to the provisioning team? I am not sure if this model is still being produced. But dedede is one of the early programs where fw_config is common to all the models and I know new models are still getting added to the dedede program.
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David Hendricks has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83327?usp=email )
Change subject: mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info
......................................................................
Patch Set 3: Code-Review-1
(1 comment)
File src/mainboard/intel/beechnutcity_crb/Kconfig:
https://review.coreboot.org/c/coreboot/+/83327/comment/b7fa84cf_f368dc0e?us… :
PS3, Line 21: config CARDBUS_PLUGIN_SUPPORT
Redundant with the above config option.
Also, why is this an option? I thought cardbus was long obsolete, and I don't see it mentioned in any BHS documents. Maybe I'm thinking of the wrong thing...
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