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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
intel/alderlake: Add helper functions for Power Management
Clock Power Management, ASPM and L1 Substates have been
configured the same way since SkyLake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.
Despite the UPDs remaining the same since SkyLake, this is not the
case for AlderLake, RaptorLake and MeteorLake.
Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.
On CometLake, this results in the correct configuration, verified
with the lspci command:
```
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On RaptorLake:
```
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```
Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.
Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.
Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 111 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81638/17
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I'd like you to reexamine a change. Please visit
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Change subject: payloads/iPXE: Add an option for reproducible building
......................................................................
payloads/iPXE: Add an option for reproducible building
Allows to set a custom 32 bit hex build_id option for an iPXE build.
Useful for reproducibility.
Change-Id: I926b096e77a9d45ba2beecd1fc2b7d0a9b9a7b9c
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
M payloads/external/Makefile.mk
M payloads/external/iPXE/Kconfig
M payloads/external/iPXE/Makefile
3 files changed, 21 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/82039/9
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Change subject: payloads/external/Makefile.mk: build iPXE for EDK2 with custom boot option name
......................................................................
Patch Set 5:
(1 comment)
File payloads/external/edk2/Makefile:
https://review.coreboot.org/c/coreboot/+/82721/comment/529c5183_849e0164?us… :
PS3, Line 152: The Dasharo repository has the following additional options:
> Could you elaborate further on this? Do you mean that this part cant be upstreamed?
I was following the convention of MrChromebox above - I'm not sure Tianocore or MrChromebox would be able to handle this functionality properly, so I've marked the following as Dasharo downstream-specific additional options.
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 16: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81638/comment/6d5625dc_3eb97469?us… :
PS15, Line 507: if (rp_cfg->pcie_rp_aspm == 0)
: s_cfg->PcieRpAspm[index] = 4;
: else
: s_cfg->PcieRpAspm[index] = rp_cfg->pcie_rp_aspm - 1;
> I don't hate it, it's certainly much more readable. […]
I added the prefix because there's functions elsewhere (common code?) with the same name.
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Change subject: ec/google/chromeec: Drop 'choice' selections for EC and PD firmware
......................................................................
Patch Set 3: Code-Review+2
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Change subject: ec/google/chromeec: Drop ability to build Chrome-EC, PD components
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/*/root_complex: introduce and use domain_iohc_info struct
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibility
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> FWIW, Karthik just mentioned that the numbers in alderlake/Kconfig are actually wrong, and the FSP on that platform only requires 256K stack according to Intel's FSP integration guide (not 512K as the Kconfig help text says). It would be good if we could double-check all platforms to ensure our documentation is accurate.
>
> Do we have an FSP integration guide for MeteorLake as well? I couldn't find one on Drive. If the number there is also smaller than 512K maybe this patch isn't that necessary (it still shouldn't hurt, though).
Please look at my CL https://review.coreboot.org/c/coreboot/+/47837 , coreboot code for ADL/MTL is correct and FSP integration guide might not have the latest requirement captured. We shall bring this into FSP sync meeting.
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