coreboot-gerrit July 2024

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[XS] Change in coreboot[main]: soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibi...
by Julius Werner (Code Review) 25 Jul '24

25 Jul '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthikeyan Ramasubramanian, Nico Huber, Paul Menzel, Rishika Raj, Subrata Banik, Tarun. Julius Werner has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email ) Change subject: soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibility ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: FWIW, Karthik just mentioned that the numbers in alderlake/Kconfig are actually wrong, and the FSP on that platform only requires 256K stack according to Intel's FSP integration guide (not 512K as the Kconfig help text says). It would be good if we could double-check all platforms to ensure our documentation is accurate. Do we have an FSP integration guide for MeteorLake as well? I couldn't find one on Drive. If the number there is also smaller than 512K maybe this patch isn't that necessary (it still shouldn't hurt, though). -- To view, visit https://review.coreboot.org/c/coreboot/+/83540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Gerrit-Change-Number: 83540 Gerrit-PatchSet: 8 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 24 Jul 2024 23:04:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/amd/common/block/psp_gen2: add get_psp_mmio_base
by Felix Held (Code Review) 25 Jul '24

25 Jul '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83446?usp=email ) Change subject: soc/amd/common/block/psp_gen2: add get_psp_mmio_base ...................................................................... Patch Set 3: (2 comments) File src/soc/amd/common/block/psp/psp_gen2.c: https://review.coreboot.org/c/coreboot/+/83446/comment/9c43d1e3_1399d45d?us… : PS2, Line 32: form > from Done https://review.coreboot.org/c/coreboot/+/83446/comment/9e7b5b55_30914be7?us… : PS2, Line 62: /* Don't cache the PSP MMIO base if the register isn't locked */ > with caching i mean put it into a static variable so that we don't have to do the lookup of the psp […] after some discussion we agreed that it would be an option to just lock the register when it's enabled, but not locked yet. this case shouldn't ever happen, but better be safe -- To view, visit https://review.coreboot.org/c/coreboot/+/83446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a Gerrit-Change-Number: 83446 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 24 Jul 2024 22:56:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/*/root_complex: introduce and use domain_iohc_info struct
by Felix Held (Code Review) 25 Jul '24

25 Jul '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Varshit Pandya. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83443?usp=email ) Change subject: soc/amd/*/root_complex: introduce and use domain_iohc_info struct ...................................................................... Patch Set 2: (2 comments) File src/soc/amd/common/block/root_complex/root_complex.c: https://review.coreboot.org/c/coreboot/+/83443/comment/cb3c3370_d3fac73a?us… : PS1, Line 15: domain->path.domain.domain > ah, no, that one does something different CB:83644 https://review.coreboot.org/c/coreboot/+/83443/comment/9af2348b_10d606b4?us… : PS1, Line 34: signed int > The fabric ID is a uint32_t, so why use a signed int for the return type? Looking at the ID values, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifce3d2b540d14ba3cba36f7cbf248fb7c63483fe Gerrit-Change-Number: 83443 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 24 Jul 2024 22:55:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: [WIP] device: introduce and use dev_get_domain_id
by Felix Held (Code Review) 25 Jul '24

25 Jul '24

Attention is currently required from: Arthur Heymans, Christian Walter, Fred Reitberger, Jason Glenesk, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Patrick Rudolph, Shuo Liu, Tim Chu, Varshit Pandya. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83644?usp=email ) Change subject: [WIP] device: introduce and use dev_get_domain_id ...................................................................... [WIP] device: introduce and use dev_get_domain_id To avoid having constructs like 'dev->path.domain.domain' in the SoC code, create the 'dev_get_domain_id' helper function that returns the domain ID of either that device if it's a domain device or the corresponding domain device's domain ID, and use it in the code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288 --- M src/device/device_util.c M src/include/device/device.h M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/data_fabric/pci_segment_multi.c M src/soc/amd/common/block/data_fabric/pci_segment_single.c M src/soc/amd/genoa_poc/domain.c M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/chip_gen6.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 11 files changed, 25 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/83644/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 2e97ece..e146950 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -261,6 +261,16 @@ return NULL; } +unsigned int dev_get_domain_id(const struct device *dev) +{ + const struct device *domain_dev = dev_get_domain(dev); + + if (!domain_dev) + die("%s: doesn't have a domain device\n", dev_path(dev)); + + return domain_dev->path.domain.domain; +} + bool is_domain0(const struct device *dev) { return dev && dev->path.type == DEVICE_PATH_DOMAIN && dev->path.domain.domain == 0; diff --git a/src/include/device/device.h b/src/include/device/device.h index ac8a117..3eee321 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -183,6 +183,7 @@ const char *dev_path(const struct device *dev); u32 dev_path_encode(const struct device *dev); const struct device *dev_get_domain(const struct device *dev); +unsigned int dev_get_domain_id(const struct device *dev); void dev_set_enabled(struct device *dev, int enable); void disable_children(struct bus *bus); bool dev_is_active_bridge(struct device *dev); diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index c419fe0..12a7bba 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -22,7 +22,7 @@ if (segment_group >= PCI_SEGMENT_GROUP_COUNT) { printk(BIOS_ERR, "Skipping domain %u due to too large segment group %u.\n", - domain->path.domain.domain, segment_group); + dev_get_domain_id(domain), segment_group); return; } diff --git a/src/soc/amd/common/block/data_fabric/pci_segment_multi.c b/src/soc/amd/common/block/data_fabric/pci_segment_multi.c index bc680f9..433b004 100644 --- a/src/soc/amd/common/block/data_fabric/pci_segment_multi.c +++ b/src/soc/amd/common/block/data_fabric/pci_segment_multi.c @@ -29,6 +29,6 @@ } printk(BIOS_ERR, "No valid DF PCI CFG register pair found for domain %x.\n", - domain->path.domain.domain); + dev_get_domain_id(domain)); return CB_ERR; } diff --git a/src/soc/amd/common/block/data_fabric/pci_segment_single.c b/src/soc/amd/common/block/data_fabric/pci_segment_single.c index 3e02d96..49e6b9a 100644 --- a/src/soc/amd/common/block/data_fabric/pci_segment_single.c +++ b/src/soc/amd/common/block/data_fabric/pci_segment_single.c @@ -27,6 +27,6 @@ } printk(BIOS_ERR, "No valid DF PCI CFG register found for domain %x.\n", - domain->path.domain.domain); + dev_get_domain_id(domain)); return CB_ERR; } diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 88f386c..b6369a4 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -26,7 +26,7 @@ { if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n", - domain->path.domain.domain); + dev_get_domain_id(domain)); const union df_vga_en vga_en = { .ve = 1, .dst_fabric_id = get_iohc_fabric_id(domain), @@ -48,6 +48,7 @@ static const char *genoa_domain_acpi_name(const struct device *domain) { + const unsigned int domain_id = dev_get_domain_id(domain); const char *domain_acpi_names[4] = { "S0B0", "S0B1", @@ -55,8 +56,8 @@ "S0B3", }; - if (domain->path.domain.domain < ARRAY_SIZE(domain_acpi_names)) - return domain_acpi_names[domain->path.domain.domain]; + if (domain_id < ARRAY_SIZE(domain_acpi_names)) + return domain_acpi_names[domain_id]; return NULL; } diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index f66f5e9..e5cf907 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -95,7 +95,7 @@ void iio_domain_set_acpi_name(struct device *dev, const char *prefix) { const union xeon_domain_path dn = { - .domain_path = dev->path.domain.domain + .domain_path = dev_get_domain_id(dev) }; assert(dn.socket < CONFIG_MAX_SOCKET); diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index d0eab02..5878ae6 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -49,7 +49,7 @@ return 0; union xeon_domain_path dn; - dn.domain_path = domain->path.domain.domain; + dn.domain_path = dev_get_domain_id(domain); if (socket != XEONSP_SOCKET_MAX && dn.socket != socket) return 0; @@ -140,7 +140,7 @@ if (!domain) return -1; - dn.domain_path = domain->path.domain.domain; + dn.domain_path = dev_get_domain_id(domain)); return dn.socket; } @@ -162,7 +162,7 @@ if (!domain) return -1; - dn.domain_path = domain->path.domain.domain; + dn.domain_path = dev_get_domain_id(domain); return dn.stack; } diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index a68c764..ee167e2 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -17,7 +17,7 @@ { assert(dev->path.type == DEVICE_PATH_DOMAIN); const union xeon_domain_path dn = { - .domain_path = dev->path.domain.domain + .domain_path = dev_get_domain_id(dev) }; const IIO_UDS *hob = get_iio_uds(); diff --git a/src/soc/intel/xeon_sp/chip_gen6.c b/src/soc/intel/xeon_sp/chip_gen6.c index 686b3e4..d53b231 100644 --- a/src/soc/intel/xeon_sp/chip_gen6.c +++ b/src/soc/intel/xeon_sp/chip_gen6.c @@ -16,7 +16,7 @@ { assert(dev->path.type == DEVICE_PATH_DOMAIN); const union xeon_domain_path dn = { - .domain_path = dev->path.domain.domain + .domain_path = dev_get_domain_id(dev) }; const IIO_UDS *hob = get_iio_uds(); diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 609ac55..b371034 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -128,7 +128,7 @@ static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev) { static uint32_t slot_num; - const uint32_t domain = dev->upstream->dev->path.domain.domain; + const uint32_t domain = dev_get_domain_id(dev); const uint32_t devfn = dev->path.pci.devfn; const struct vendorcode_amd_opensil_chip_mpio_config *const config = dev->chip_info; printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/83644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288 Gerrit-Change-Number: 83644 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: acpi,soc: use is_domain0 function
by Felix Held (Code Review) 25 Jul '24

25 Jul '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Fred Reitberger, Jason Glenesk, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Shuo Liu, Tim Chu, Tim Wawrzynczak. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83643?usp=email ) Change subject: acpi,soc: use is_domain0 function ...................................................................... acpi,soc: use is_domain0 function No need to open-code this when we have a function for this. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iae570ba750cb29456436349b4263808e2e410e2e --- M src/acpi/acpigen_pci_root_resource_producer.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/xeon_sp/uncore_acpi.c 4 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/83643/1 diff --git a/src/acpi/acpigen_pci_root_resource_producer.c b/src/acpi/acpigen_pci_root_resource_producer.c index 78e1a89..ce57b9cc 100644 --- a/src/acpi/acpigen_pci_root_resource_producer.c +++ b/src/acpi/acpigen_pci_root_resource_producer.c @@ -60,7 +60,7 @@ acpigen_resource_producer_bus_number(domain->downstream->secondary, domain->downstream->max_subordinate); - if (domain->path.domain.domain == 0) { + if (is_domain0(domain)) { /* ACPI 6.4.2.5 I/O Port Descriptor */ acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, PCI_IO_CONFIG_PORT_COUNT, 1); diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index b056d60..c419fe0 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -206,7 +206,7 @@ read_non_pci_resources(domain, &idx); /* Only add the SoC's DRAM memory map and fixed resources once */ - if (domain->path.domain.domain == 0) { + if (is_domain0(domain)) { add_pci_cfg_resources(domain, &idx); read_soc_memmap_resources(domain, &idx); diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 81c9a64..e0caea6 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -386,8 +386,7 @@ static void enable_soc_dev(struct device *dev) { - if (dev->path.type == DEVICE_PATH_DOMAIN && - dev->path.domain.domain == 0) { + if (is_domain0(dev)) { dev->ops = &pci_domain_ops_ecam0; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &soc_ops; diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 22f8b6f..0b2b9f4 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -560,7 +560,7 @@ struct acpi_rsdp *rsdp) { /* Only write uncore ACPI tables for domain0 */ - if (device->path.domain.domain != 0) + if (!is_domain0(device)) return current; acpi_srat_t *srat; -- To view, visit https://review.coreboot.org/c/coreboot/+/83643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae570ba750cb29456436349b4263808e2e410e2e Gerrit-Change-Number: 83643 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: device: move is_domain0 and is_dev_on_domain0 to common code
by Felix Held (Code Review) 25 Jul '24

25 Jul '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83642?usp=email ) Change subject: device: move is_domain0 and is_dev_on_domain0 to common code ...................................................................... device: move is_domain0 and is_dev_on_domain0 to common code Move is_domain0 and is_dev_on_domain0 from the Intel Xeon SP code to the common coreboot code so that it can be used elsewhere in coreboot too, and while moving also implement it as functions instead of macros which is more in line with the rest of helper functions in that new file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I954251ebc82802c77bf897dfa2db54aa10bc5ac4 --- M src/device/device_util.c M src/include/device/device.h M src/soc/intel/xeon_sp/include/soc/chip_common.h 3 files changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/83642/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 6a45770..2e97ece 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -261,6 +261,16 @@ return NULL; } +bool is_domain0(const struct device *dev) +{ + return dev && dev->path.type == DEVICE_PATH_DOMAIN && dev->path.domain.domain == 0; +} + +bool is_dev_on_domain0(const struct device *dev) +{ + return is_domain0(dev_get_domain(dev)); +} + /** * Allocate 64 more resources to the free list. * diff --git a/src/include/device/device.h b/src/include/device/device.h index 1b2e097..ac8a117 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -194,6 +194,8 @@ bool is_enabled_pci(const struct device *pci); bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus); bool is_pci_bridge(const struct device *pci); +bool is_domain0(const struct device *dev); +bool is_dev_on_domain0(const struct device *dev); /* Returns whether there is a hotplug port on the path to the given device. */ bool dev_path_hotplug(const struct device *); diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index c5553c0..4731bec 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -83,9 +83,6 @@ #define is_dev_on_ubox_domain(dev) is_ubox_domain(dev_get_domain(dev)) #define is_dev_on_cxl_domain(dev) is_cxl_domain(dev_get_domain(dev)) -#define is_domain0(dev) (dev && dev->path.type == DEVICE_PATH_DOMAIN &&\ - dev->path.domain.domain == 0) -#define is_dev_on_domain0(dev) (is_domain0(dev_get_domain(dev))) #define is_stack0(socket, stack) (socket == 0 && stack == IioStack0) void unlock_pam_regions(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/83642?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I954251ebc82802c77bf897dfa2db54aa10bc5ac4 Gerrit-Change-Number: 83642 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/*/root_complex: introduce and use domain_iohc_info struct
by Felix Held (Code Review) 25 Jul '24

25 Jul '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Varshit Pandya. Hello Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83443?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Varshit Pandya, Code-Review+2 by Martin Roth, Verified+1 by build bot (Jenkins) Change subject: soc/amd/*/root_complex: introduce and use domain_iohc_info struct ...................................................................... soc/amd/*/root_complex: introduce and use domain_iohc_info struct Instead of implementing the functions get_iohc_misc_smn_base and get_iohc_fabric_id in the SoC code, move those functions to the common AMD code, and implement get_iohc_info in the SoC code that returns a pointer to and the size of a SoC-specific array of domain_iohc_info structs that contains the info needed by the common code instead. This allows to iterate over the domain_iohc_info structs which will be used in a later patch to find the PSP MMIO base address in both ramstage and smm. TEST=Mandolin still boots and all non-PCI MIO resources are still reported to the resource allocator Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifce3d2b540d14ba3cba36f7cbf248fb7c63483fe --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/include/amdblocks/root_complex.h M src/soc/amd/common/block/root_complex/Makefile.mk A src/soc/amd/common/block/root_complex/root_complex.c M src/soc/amd/genoa_poc/root_complex.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c 9 files changed, 122 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/83443/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifce3d2b540d14ba3cba36f7cbf248fb7c63483fe Gerrit-Change-Number: 83443 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

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[M] Change in coreboot[main]: soc/amd/common/block/psp_gen2: add get_psp_mmio_base
by Felix Held (Code Review) 25 Jul '24

25 Jul '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83446?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/common/block/psp_gen2: add get_psp_mmio_base ...................................................................... soc/amd/common/block/psp_gen2: add get_psp_mmio_base Add get_psp_mmio_base which reads the PSP MMIO base address from the hardware registers. Since this function will not only be called in ramstage, but also in SMM, we can't just look for the specific domain resource consumer like it is done for the IOAPICs in the northbridge, but have to get this base address from the registers. In order to limit the performance impact of this, the base address gets cached in a static variable if an enabled PSP MMIO base register is found. We expect that this register is locked when it was configured and enabled; if we run into the unexpected case that the PSP MMIO register is enabled, but not locked, set the lock bit of the corresponding base address register to be sure that it won't change until the next reset and that the hardware value can't be different than the cached value. This is a preparation to move back to using MMIO access to the PSP registers and will also enable cases that require the use of the MMIO mapping of the PSP registers. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a --- M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c 2 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83446/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a Gerrit-Change-Number: 83446 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

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[S] Change in coreboot[main]: arch/riscv/pmp: Add print macro
by Maximilian Brune (Code Review) 25 Jul '24

25 Jul '24

Attention is currently required from: Philipp Hug, Ron Minnich. Hello Philipp Hug, Ron Minnich, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83056?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv/pmp: Add print macro ...................................................................... arch/riscv/pmp: Add print macro This adds a printk macro in the PMP code to avoid all harts writing onto the serial which causes crappy/broken output. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Icaded168bd7302ad1ea29bebb7900810ebeff92d --- M src/arch/riscv/pmp.c 1 file changed, 17 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/83056/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaded168bd7302ad1ea29bebb7900810ebeff92d Gerrit-Change-Number: 83056 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

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[M] Change in coreboot[main]: arch/riscv: Remove opensbi submodule includes
by Maximilian Brune (Code Review) 25 Jul '24

25 Jul '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83641?usp=email ) Change subject: arch/riscv: Remove opensbi submodule includes ...................................................................... arch/riscv: Remove opensbi submodule includes Currently we include a header file from the opensbi submodule. That causes some issues, since we merge outside code with our own. Most recently there have been made attempts to make the coreboot codebase C23 ready. The code that we include from opensbi however causes the build to fail, since it is not C23 ready. This patch effectivily detaches the coreboot codebase from the opensbi codebase and just copies the structure and definitions that we need from opensbi into coreboot. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I9d8f85ee805bbbf2627ef419685440b37c15f906 --- M src/arch/riscv/Makefile.mk M src/arch/riscv/opensbi.c 2 files changed, 34 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/83641/1 diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk index d5defea..6754c22 100644 --- a/src/arch/riscv/Makefile.mk +++ b/src/arch/riscv/Makefile.mk @@ -180,7 +180,6 @@ check-ramstage-overlap-files += $(OPENSBI_CBFS) -CPPFLAGS_common += -I$(OPENSBI_SOURCE)/include ramstage-y += opensbi.c endif #CONFIG_RISCV_OPENSBI diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c index bf26b22..36f2951 100644 --- a/src/arch/riscv/opensbi.c +++ b/src/arch/riscv/opensbi.c @@ -1,13 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* OpenSBI wants to make its own definitions for some of our compiler.h macros. */ -#undef __packed -#undef __noreturn -#undef __aligned - -#include <sbi/fw_dynamic.h> #include <arch/boot.h> -/* DO NOT INCLUDE COREBOOT HEADERS HERE */ +#include <arch/encoding.h> +#include <stdint.h> +#include <stddef.h> + +#define FW_DYNAMIC_INFO_VERSION_2 2 +#define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f // "OSBI" + +/* + * structure passed to OpenSBI as 3rd argument + * NOTE: This structure may need to be updated when the OpenSBI submodule is updated. + */ +static struct __packed fw_dynamic_info { + unsigned long magic; // magic value "OSBI" + unsigned long version; // version number (2) + unsigned long next_addr; // Next booting stage address (payload address) + unsigned long next_mode; // Next booting stage mode (usually supervisor mode) + unsigned long options; // options for OpenSBI library + unsigned long boot_hart; // usually CONFIG_RISCV_WORKING_HARTID +} info; void run_opensbi(const int hart_id, const void *fdt, @@ -15,21 +27,21 @@ const void *payload, const int payload_mode) { - struct fw_dynamic_info info = { - .magic = FW_DYNAMIC_INFO_MAGIC_VALUE, - .version = FW_DYNAMIC_INFO_VERSION_MAX, - .next_mode = payload_mode, - .next_addr = (uintptr_t)payload, - .options = 0, - .boot_hart = CONFIG_OPENSBI_FW_DYNAMIC_BOOT_HART, - }; + info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE, + info.version = FW_DYNAMIC_INFO_VERSION_2, + info.next_mode = payload_mode, + info.next_addr = (uintptr_t)payload, + info.options = 0, + info.boot_hart = CONFIG_OPENSBI_FW_DYNAMIC_BOOT_HART, - csr_write(mepc, opensbi); + write_csr(mepc, opensbi); // set program counter to OpenSBI (jumped to with mret) asm volatile ( - "mv a0, %0\n\t" - "mv a1, %1\n\t" - "mv a2, %2\n\t" - "mret" : - : "r"(hart_id), "r"(fdt), "r"(&info) - : "a0", "a1", "a2"); + "mv a0, %0\n\t" + "mv a1, %1\n\t" + "mv a2, %2\n\t" + "mret" + : + : "r"(hart_id), "r"(fdt), "r"(&info) + : "a0", "a1", "a2" + ); } -- To view, visit https://review.coreboot.org/c/coreboot/+/83641?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9d8f85ee805bbbf2627ef419685440b37c15f906 Gerrit-Change-Number: 83641 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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