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Change subject: commonlib/device_tree.c: Add read reg property helper
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
File src/commonlib/device_tree.c:
https://review.coreboot.org/c/coreboot/+/83457/comment/ada15584_ec192436?us… :
PS3, Line 1013: size_t count = prop->prop.size / (4 * addr_cells + 4 * size_cells);
> like this?
Yeah, like this, thanks!
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Change subject: bootsplash: Increase heap from 1 MB to 4 MB when bootsplash is enabled
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
> Is 4 MB so large to be problematic? I'm familiar with Wuffs but not so familiar with coreboot. […]
I don't have a problem with 4 MB. I don't think it'd be a problem anywhere (I don't think coreboot supports anything old enough for 4 MB to be an appreciable chunk of RAM), but I'm not familiar enough with every board and chipset to be sure.
I can certainly raise the default heap from 1 MB to 4 MB without depending on the bootsplash config if we agree that's reasonable. Any objections?
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/83476/comment/f8a2531a_505051fe?us… :
PS2, Line 507: default 0x400000 if BOOTSPLASH
> Why not adding this as another default to src/Kconfig?
I can move it over there, I don't really have a preference
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Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83572/comment/5af7b4e9_9a707011?us… :
PS4, Line 9: Add new folder and basic drivers for Mediatek SoC 'MT8196'.
> Jarried, why did you mark it as done without improving the commit message. […]
At the leadership meeting, Julius answered, the MT8195 and MT8196 are very different, so having a new directory is warranted.
PS: Most attendees also agreed, if a reviewer asks to be more elaborate, that one should try to address that, especially if it’s not much trouble. Still both sides should be polite, so I am sorry, if I was not. Thank you for working on coreboot!
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Change subject: 3rdparty: Remove chromeec submodule
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Patch Set 5: Code-Review+1
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Change subject: 3rdparty: Remove chromeec submodule
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Patchset:
PS5:
let's remove the references in chromeec and mainboards first:
config EC_GOOGLE_CHROMEEC_BOARDNAME
config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
config EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_BUILTIN
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Change subject: soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU
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Patch Set 1: Code-Review+2
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 15:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81638/comment/2007fe19_ae00527e?us… :
PS15, Line 507: if (rp_cfg->pcie_rp_aspm == 0)
: s_cfg->PcieRpAspm[index] = 4;
: else
: s_cfg->PcieRpAspm[index] = rp_cfg->pcie_rp_aspm - 1;
> I feel like we should be using an enum here rather than int values which are hard to parse
That too
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Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
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Patch Set 9: Code-Review+2
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 15:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81638/comment/71b25d34_99a94412?us… :
PS15, Line 507: if (rp_cfg->pcie_rp_aspm == 0)
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: else
: s_cfg->PcieRpAspm[index] = rp_cfg->pcie_rp_aspm - 1;
> I would make a helper function for this: […]
I feel like we should be using an enum here rather than int values which are hard to parse
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