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Change subject: arch/arm64/armv8/mmu: Improve log format
......................................................................
arch/arm64/armv8/mmu: Improve log format
When using format string with "%p", "(nil)" will be printed for address
0. To improve readability of the printed addresses in the log, change
the format to "0x%013lx", so that the length of the printed addresses
will be consistent.
In addition, print the level of the translation table when setting up a
new table.
Example log:
Backing address range [0x0000000000000:0x1000000000000) with new L0 ...
Mapping address range [0x0000000000000:0x0000200000000) as ...
Backing address range [0x0000000000000:0x0008000000000) with new L1 ...
Mapping address range [0x0000000100000:0x0000000130000) as ...
Backing address range [0x0000000000000:0x0000040000000) with new L2
Backing address range [0x0000000000000:0x0000000200000) with new L3
Mapping address range [0x0000000107000:0x0000000108000) as ...
Mapping address range [0x0000000200000:0x0000000300000) as ...
Backing address range [0x0000000000000:0x0000000200000) with new L3 ...
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: Ib29c201e1b096b9c7cd750d2541923616bc858ac
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/arch/arm64/armv8/mmu.c
1 file changed, 30 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83652/1
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 0f84146..65d0f92 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -11,6 +11,9 @@
#include <arch/mmu.h>
#include <console/console.h>
+/* 12 hex digits (48 bits VA) plus 1 for exclusive upper bound. */
+#define ADDR_FMT "0x%013lx"
+
/* This just caches the next free table slot (okay to do since they fill up from
* bottom to top and can never be freed up again). It will reset to its initial
* value on stage transition, so we still need to check it for UNUSED_DESC. */
@@ -54,6 +57,25 @@
return attr;
}
+/* Func : table_level_name
+ * Desc : Get the descriptions table level name from the given size.
+ */
+static const char *table_level_name(size_t xlat_size)
+{
+ switch (xlat_size) {
+ case L0_XLAT_SIZE:
+ return "L0";
+ case L1_XLAT_SIZE:
+ return "L1";
+ case L2_XLAT_SIZE:
+ return "L2";
+ case L3_XLAT_SIZE:
+ return "L3";
+ default:
+ return "";
+ }
+}
+
/* Func : setup_new_table
* Desc : Get next free table from TTB and set it up to match old parent entry.
*/
@@ -66,9 +88,12 @@
}
void *frame_base = (void *)(desc & XLAT_ADDR_MASK);
- printk(BIOS_DEBUG, "Backing address range [%p:%p) with new page"
- " table @%p\n", frame_base, frame_base +
- (xlat_size << BITS_RESOLVED_PER_LVL), next_free_table);
+ const char *level_name = table_level_name(xlat_size);
+ printk(BIOS_DEBUG,
+ "Backing address range [" ADDR_FMT ":" ADDR_FMT ") with new %s table @%p\n",
+ (uintptr_t)frame_base,
+ (uintptr_t)frame_base + (xlat_size << BITS_RESOLVED_PER_LVL),
+ level_name, next_free_table);
if (!desc) {
memset(next_free_table, 0, GRANULE_SIZE);
@@ -213,8 +238,8 @@
uint64_t base_addr = (uintptr_t)start;
uint64_t temp_size = size;
- printk(BIOS_INFO, "Mapping address range [%p:%p) as ",
- start, start + size);
+ printk(BIOS_INFO, "Mapping address range [" ADDR_FMT ":" ADDR_FMT ") as ",
+ (uintptr_t)start, (uintptr_t)start + size);
print_tag(BIOS_INFO, tag);
sanity_check(base_addr, temp_size);
--
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Gerrit-Change-Number: 83652
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Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83651?usp=email )
Change subject: arch/arm64/armv8/mmu: Add missing header arch/barrier.h
......................................................................
arch/arm64/armv8/mmu: Add missing header arch/barrier.h
Also take the chance to sort the headers.
BUG=none
TEST=none
BRANCH=none
Change-Id: I9d487a40d0c58c6458b8b7d32b6401093fa417e7
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/arch/arm64/armv8/mmu.c
1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/83651/1
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 6105f9a..0f84146 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -5,10 +5,11 @@
#include <string.h>
#include <symbols.h>
-#include <console/console.h>
-#include <arch/mmu.h>
-#include <arch/lib_helpers.h>
+#include <arch/barrier.h>
#include <arch/cache.h>
+#include <arch/lib_helpers.h>
+#include <arch/mmu.h>
+#include <console/console.h>
/* This just caches the next free table slot (okay to do since they fill up from
* bottom to top and can never be freed up again). It will reset to its initial
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Change subject: soc/mediatek/mt8188/memlayout: Fix a space in SRAM_L2C_START comment
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK comment
......................................................................
Patch Set 1: Code-Review+2
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Change subject: device: move is_domain0 and is_dev_on_domain0 to common code
......................................................................
Patch Set 1: Code-Review+1
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Change subject: acpi,soc: use is_domain0 function
......................................................................
Patch Set 1: Code-Review+1
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Change subject: payloads/external/Makefile.mk: build iPXE for EDK2 with custom boot option name
......................................................................
Patch Set 5:
(1 comment)
File payloads/external/edk2/Makefile:
https://review.coreboot.org/c/coreboot/+/82721/comment/05a81be2_f52dc915?us… :
PS3, Line 152: The Dasharo repository has the following additional options:
> I was following the convention of MrChromebox above - I'm not sure Tianocore or MrChromebox would be […]
that is true. What i meant is, like MrCrhomebox or any other repos, there are included as part of kconfig to switch to that specific repo.
Could you follow the similar pattern from MrChromebox to create this kconfig (EDK2_REPO_DASHARO or something similar), and guard this with this kconfig?
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Attention is currently required from: Angel Pons, Dinesh Gehlot, Eric Lai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Nico Huber, Paul Menzel, Sean Rhodes, Subrata Banik.
Hello Angel Pons, Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81638?usp=email
to look at the new patch set (#21).
The following approvals got outdated and were removed:
Code-Review+1 by Angel Pons
Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
intel/alderlake: Add helper functions for Power Management
Clock Power Management, ASPM and L1 Substates have been
configured the same way since SkyLake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.
Despite the UPDs remaining the same since SkyLake, this is not the
case for AlderLake, RaptorLake and MeteorLake.
Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.
On CometLake, this results in the correct configuration, verified
with the lspci command:
```
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On RaptorLake:
```
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```
Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.
Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.
Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 88 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81638/21
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