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Hello Angel Pons, Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#22).
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Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)
Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
intel/alderlake: Add helper functions for Power Management
Clock Power Management, ASPM and L1 Substates have been
configured the same way since Skylake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.
Despite the UPDs remaining the same since Skylake, this is not the
case for Alderlake, Raptorlake and Meteorlake.
Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.
On Cometlake, this results in the correct configuration, verified
with the lspci command:
```
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On Raptorlake:
```
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```
Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.
Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.
Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 88 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81638/22
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 21:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81638/comment/d58f6e25_ca532577?us… :
PS21, Line 10: SkyLake
> I removed the space so it could be found in search
Here, Paul just wants to make the `L` lowercase: `Skylake`
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 21:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81638/comment/af1e1b0b_e6708abc?us… :
PS21, Line 10: SkyLake
> Skylake ;-) […]
I removed the space so it could be found in search
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Change subject: arch/arm64/armv8/mmu: Improve log format
......................................................................
Patch Set 2:
(1 comment)
File src/arch/arm64/armv8/mmu.c:
https://review.coreboot.org/c/coreboot/+/83652/comment/354c3df7_ba0eed2f?us… :
PS2, Line 60: /* Func : table_level_name
: * Desc : Get the descriptions table level name from the given size.
: */
Unrelated: Not one of the recommended multi-line comment styles.
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 21:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81638/comment/518e1203_22005657?us… :
PS21, Line 10: SkyLake
Skylake ;-)
https://en.wikipedia.org/wiki/Skylake_(microarchitecture)https://review.coreboot.org/c/coreboot/+/81638/comment/0125b2a2_93deaea1?us… :
PS21, Line 14: SkyLake
Ditto.
https://review.coreboot.org/c/coreboot/+/81638/comment/88b84072_cea61438?us… :
PS21, Line 15: AlderLake, RaptorLake and MeteorLake
Official spelling has a space.
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Change subject: arch/arm64/armv8/mmu: Add missing header arch/barrier.h
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/mediatek/mt8188/memlayout: Fix a space in SRAM_L2C_START comment
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83650/comment/3400f70b_eda180c7?us… :
PS1, Line 7: Fix
Add
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Change subject: soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK comment
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Should the comment be reworded for the other SOCs too?
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Change subject: device: move is_domain0 and is_dev_on_domain0 to common code
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Patch Set 1: Code-Review+1
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Change subject: acpi,soc: use is_domain0 function
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