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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,262 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/15
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Change subject: acpi,soc: use is_domain0 function
......................................................................
Patch Set 1: Code-Review+2
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Change subject: device: move is_domain0 and is_dev_on_domain0 to common code
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Patch Set 1: Code-Review+2
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Change subject: mb/novacustom: add V5x0TU board (Meteor Lake)
......................................................................
Patch Set 13:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82673/comment/f8a4db32_15ac420d?us… :
PS8, Line 28: - DDR5 SODIMM in slot RAM1
> I've updated CB:52731 and uploaded CB:82733 for this.
Thanks, those patches did help
File src/mainboard/novacustom/mtl-h/romstage.c:
https://review.coreboot.org/c/coreboot/+/82673/comment/6d127381_ed5b46af?us… :
PS8, Line 23:
> LpDdrDqDqsReTraining may sometimes help with training
Wasn't needed after all. There were 2 issues:
- SPD reading, Tim's patches helped
- I tested with different DIMMs that produced the same SPD checksum due to missing serial numbers, causing FSP to consider them the same and mistakenly try MRC fast boot instead of triggering retraining.
File src/mainboard/novacustom/mtl-h/vboot-rwab.fmd:
https://review.coreboot.org/c/coreboot/+/82673/comment/e2b4122e_dad7c314?us… :
PS8, Line 11: RW_FWID_A 64
> 64 bytes often occurs to be too small. […]
Done
https://review.coreboot.org/c/coreboot/+/82673/comment/b6342a27_89d0f5a5?us… :
PS8, Line 41: RO_GSCVD 8K
> Do we need this?
Nope, removed
https://review.coreboot.org/c/coreboot/+/82673/comment/6e6df9a6_0fc53dea?us… :
PS8, Line 44: RO_FRID 64
> a/a, use 256
Done
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Hello Krystian Hebel, Maciej Pijanowski, Michał Żygowski, build bot (Jenkins),
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Change subject: mb/novacustom: add V5x0TU board (Meteor Lake)
......................................................................
mb/novacustom: add V5x0TU board (Meteor Lake)
NovaCustom (Clevo) V5x0TU are two boards with Intel Core Ultra (Meteor
Lake) series processors.
Two variants (V540TU and V560TU) are supported. Their EC firmware is
different due to keyboard layout changes. On coreboot's side, the only
difference are SMBIOS strings.
Working:
- DDR5 SODIMM in slot RAM2
- M.2 2280 PCIe slots
- Thunderbolt, USB ports
- Video outputs in OS and firmware
- I2C touchpad, webcam, SD Card reader
- S0ix
- Booting Ubuntu 24.04 with edk2 UefiPayload
- Vboot, TPM measured boot
Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
A src/mainboard/novacustom/Kconfig
A src/mainboard/novacustom/Kconfig.name
A src/mainboard/novacustom/mtl-h/Kconfig
A src/mainboard/novacustom/mtl-h/Kconfig.name
A src/mainboard/novacustom/mtl-h/Makefile.mk
A src/mainboard/novacustom/mtl-h/acpi/backlight.asl
A src/mainboard/novacustom/mtl-h/acpi/mainboard.asl
A src/mainboard/novacustom/mtl-h/board_info.txt
A src/mainboard/novacustom/mtl-h/bootblock.c
A src/mainboard/novacustom/mtl-h/cmos.default
A src/mainboard/novacustom/mtl-h/cmos.layout
A src/mainboard/novacustom/mtl-h/data.vbt
A src/mainboard/novacustom/mtl-h/devicetree.cb
A src/mainboard/novacustom/mtl-h/dsdt.asl
A src/mainboard/novacustom/mtl-h/fadt.c
A src/mainboard/novacustom/mtl-h/gpio.c
A src/mainboard/novacustom/mtl-h/gpio_early.c
A src/mainboard/novacustom/mtl-h/hda_verb.c
A src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h
A src/mainboard/novacustom/mtl-h/ramstage.c
A src/mainboard/novacustom/mtl-h/romstage.c
A src/mainboard/novacustom/mtl-h/vboot-rwab.fmd
22 files changed, 1,395 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/82673/14
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Change subject: mb/intel/beechnutcity_crb: Update SMBIOS info for type 0,1,2,3
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Patch Set 6: Code-Review+2
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Change subject: mb/intel/avenuecity_crb: Update SMBIOS info for type 0,1,2,3
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Patch Set 6: Code-Review+2
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Change subject: soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory
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Patch Set 1: Code-Review+1
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 22:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81638/comment/32dd2b06_76da4eb0?us… :
PS21, Line 10: SkyLake
> Here, Paul just wants to make the `L` lowercase: `Skylake`
Done
https://review.coreboot.org/c/coreboot/+/81638/comment/0cced54a_17156504?us… :
PS21, Line 14: SkyLake
> Ditto.
Done
https://review.coreboot.org/c/coreboot/+/81638/comment/052c2298_3244be0f?us… :
PS21, Line 15: AlderLake, RaptorLake and MeteorLake
> Official spelling has a space.
Done
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