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I'd like you to reexamine a change. Please visit
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Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)
Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
intel/alderlake: Add helper functions for Power Management
Clock Power Management, ASPM and L1 Substates have been
configured the same way since SkyLake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.
Despite the UPDs remaining the same since SkyLake, this is not the
case for AlderLake, RaptorLake and MeteorLake.
Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.
On CometLake, this results in the correct configuration, verified
with the lspci command:
```
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On RaptorLake:
```
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```
Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.
Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.
Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 88 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81638/20
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Angel Pons has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/81638?usp=email )
Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 19: Code-Review+1
(2 comments)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81638/comment/571daa2a_fead5756?us… :
PS15, Line 507: if (rp_cfg->pcie_rp_aspm == 0)
: s_cfg->PcieRpAspm[index] = 4;
: else
: s_cfg->PcieRpAspm[index] = rp_cfg->pcie_rp_aspm - 1;
> Done
Looks good to me. I just noticed that `!CONFIG(PCIEXP_ASPM)` could also be factored in, but your choice.
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81638/comment/0e854664_6e945fec?us… :
PS19, Line 509: complaince
typo: compliance
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Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83650?usp=email )
Change subject: soc/mediatek/mt8188/memlayout: Fix a space in SRAM_L2C_START comment
......................................................................
soc/mediatek/mt8188/memlayout: Fix a space in SRAM_L2C_START comment
Change-Id: I1888fedcc66ae13c76331d3f2f4465197ae51d35
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/mediatek/mt8188/include/soc/memlayout.ld
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/83650/1
diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
index 3dc386e..732b5ba 100644
--- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
@@ -29,7 +29,7 @@
/*
* The L3 is 2MB in total. The bootROM has configured half of the L3 cache as SRAM
- *(SRAM_L2C) so that's 1MB (and the rest to be cache, which is required so you
+ * (SRAM_L2C) so that's 1MB (and the rest to be cache, which is required so you
* can't reconfigure whole L3 as SRAM).
*/
SRAM_L2C_START(0x00200000)
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Change subject: soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK comment
......................................................................
soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK comment
The comment for the BOOTBLOCK region should be written right above the
BOOTBLOCK declaration.
BUG=b:317009620
TEST=none
BRANCH=none
Change-Id: I7afdf74844a9d97169b4e4a23c3c9c6060e886d9
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/mediatek/mt8196/include/soc/memlayout.ld
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/83649/1
diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
index e0975c7..664e55b 100644
--- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
@@ -40,8 +40,8 @@
* aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz
*/
DRAM_INIT_CODE(0x02000000, 600K)
- /* 4K reserved for BOOTROM until BOOTBLOCK is started */
#else
+ /* The beginning 4K of SRAM_L2C is reserved for BOOTROM until BOOTBLOCK is started. */
BOOTBLOCK(0x02001000, 60K)
#endif
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K)
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Attention is currently required from: Máté Kukri.
Nico Huber has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/81529?usp=email )
Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/dell/optiplex_9020/mainboard.c:
https://review.coreboot.org/c/coreboot/+/81529/comment/dfc61416_515212fb?us… :
PS11, Line 310: / rapl_power_unit
Coverity reported this a while ago, wasn't sure what's right to do so didn't
fix it, forgot about it ._. and now noticed again.
There's actually a potential divide-by-zero on all paths:
1. When it's `0` from the beginning (the `if` doesn't trigger)
2. When the MSR value is `> 7`, storing the result in the `uint8_t` makes it `0`.
Hmmm, and now I realize that it's actually not that complicated, but please
check my reasoning:
1. Can be avoided by making it simply `rapl_power_unit = 1 << rapl_power_unit;`, no `if`. Also seems more cannonical.
2. Never use fixed-width types unless you have to. Using `unsigned int` everywhere inside this function would avoid potential overflows.
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 14:
(1 comment)
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/c625061b_9dfc63f2?us… :
PS8, Line 37: VTD_BASE_ADDRESS
> > Subrata, VTD_BASE_ADDRESS is required, for IOMMU, followed by gfx, non-gfx of 64KB size,so you are […]
I checked with latest HAS July release doc, DMI3BAR is Not used for PTL Mobile.
But, we hace a VTD BAR , BIOS is responsible to expose the IOMMU as Remapping Hardware unit through DMAR (DMA remapping) ACPI tables to the Operating system.
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 14:
(8 comments)
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/65123cec_e21e4eb8?us… :
PS14, Line 10: */
Please add a new line here.
File src/soc/intel/pantherlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/58961eac_a903f3cd?us… :
PS14, Line 9: #if !defined(__SIMPLE_DEVICE__)
Suggestion:
Please align this #if flow with #if in line 19 below.
i.e. use #if defined() in both, instead of mixing.
Easier to read.
https://review.coreboot.org/c/coreboot/+/83354/comment/73e9888c_1e9e23ae?us… :
PS14, Line 165: #define PCI_DEVFN_PCIE7 _PCI_DEVFN(PCIE_1, 6)
Please fix spaces.
https://review.coreboot.org/c/coreboot/+/83354/comment/46fb5f56_d9596c0d?us… :
PS14, Line 211: #endif
Suggestion: For such nested endif, please add a comment for which #if, for better readability.
https://review.coreboot.org/c/coreboot/+/83354/comment/c8e2b804_54b493e1?us… :
PS14, Line 219: #endif
Same as line 211 above.
File src/soc/intel/pantherlake/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/7d3ca966_c303459a?us… :
PS14, Line 6: /*
: * Port ids
: */
> why multiline ?
These multiline comments at file header follows is seen in earlier soc files as well, but if we use single line comments we scroll fewer 2 lines.
File src/soc/intel/pantherlake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/173884c3_a37c467e?us… :
PS14, Line 80: #define GPE_STS_RSVD GPE_STD
Do we need duplicating macros?
https://review.coreboot.org/c/coreboot/+/83354/comment/bc96212d_a0d207f3?us… :
PS14, Line 97: #define PME_B0_EN_BIT 13
If this macro is unused anywhere else, we could remove this and follow same (1 << x) as earlier lines. If required, we can add a comment.
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