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Hello Angel Pons, Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#19).
Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
intel/alderlake: Add helper functions for Power Management
Clock Power Management, ASPM and L1 Substates have been
configured the same way since SkyLake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.
Despite the UPDs remaining the same since SkyLake, this is not the
case for AlderLake, RaptorLake and MeteorLake.
Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.
On CometLake, this results in the correct configuration, verified
with the lspci command:
```
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On RaptorLake:
```
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```
Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.
Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.
Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 94 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81638/19
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Change subject: mb/protectli/vault_[adl_p,bsw]/Kconfig: drop unneeded MAINBOARD_VENDOR
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 14:
(1 comment)
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/dbc82114_ff773637?us… :
PS8, Line 37: VTD_BASE_ADDRESS
> Subrata, VTD_BASE_ADDRESS is required, for IOMMU, followed by gfx, non-gfx of 64KB size,so you are suggesting to drop it?
>
> Details below:
> FC800000-FC87FFFF 512KB VTD BAR
> 2 IOMMU's in Compute ( gfx & non-gfx)
>
> 1 IOMMU on SOC die each with 64KB
I read the last comment as in VTD has renamed to DMI3BAR (6.3 of PTL FAS) which is not applicable for client hence, requested to drop.
if that is not the case, then please help to clarify.
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 18:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81638/comment/e4608aad_6b110738?us… :
PS15, Line 507: if (rp_cfg->pcie_rp_aspm == 0)
: s_cfg->PcieRpAspm[index] = 4;
: else
: s_cfg->PcieRpAspm[index] = rp_cfg->pcie_rp_aspm - 1;
> Added prefixes but will do a follow up patch to move it to common code so mtl can share. […]
Any reason not to incorporate `CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)` inside the helper functions? And `!CONFIG(PCIEXP_L1_SUB_STATE)` as well
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 18:
(3 comments)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/81638/comment/b4355d05_875968cd?us… :
PS4, Line 799: };
> Doh, it look me ages to see why - CPU ports have a different default which was what broke things for […]
Done
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81638/comment/68edf909_d18b2afe?us… :
PS15, Line 507: if (rp_cfg->pcie_rp_aspm == 0)
: s_cfg->PcieRpAspm[index] = 4;
: else
: s_cfg->PcieRpAspm[index] = rp_cfg->pcie_rp_aspm - 1;
> I added the prefix because there's functions elsewhere (common code?) with the same name.
Added prefixes but will do a follow up patch to move it to common code so mtl can share. Maybe other platforms too, if there's a way to handle not having CPU RPs
https://review.coreboot.org/c/coreboot/+/81638/comment/8ec3e67e_63c6ace9?us… :
PS15, Line 519: if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
: s_cfg->PcieRpL1Substates[index] = 0;
: else if (rp_cfg->PcieRpL1Substates == 0)
: s_cfg->PcieRpL1Substates[index] = 3;
: else
: s_cfg->PcieRpL1Substates[index] = rp_cfg->PcieRpL1Substates - 1;
> I would make a helper function for this: […]
Done
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Hello Angel Pons, Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81638?usp=email
to look at the new patch set (#18).
Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
intel/alderlake: Add helper functions for Power Management
Clock Power Management, ASPM and L1 Substates have been
configured the same way since SkyLake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.
Despite the UPDs remaining the same since SkyLake, this is not the
case for AlderLake, RaptorLake and MeteorLake.
Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.
On CometLake, this results in the correct configuration, verified
with the lspci command:
```
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On RaptorLake:
```
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```
Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.
Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.
Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 111 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81638/18
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