coreboot-gerrit July 2024

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[S] Change in coreboot[main]: cpu/intel: Add socket types
by Arthur Heymans (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Jincheng Li, Johnny Lin, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Shuo Liu. Arthur Heymans has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83329?usp=email ) Change subject: cpu/intel: Add socket types ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: This is neat. -- To view, visit https://review.coreboot.org/c/coreboot/+/83329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida3315694f3ce397b9ad9d676d3195da5f096cb7 Gerrit-Change-Number: 83329 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 03 Jul 2024 11:35:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: arch/x86: Decouple socket type from SoC type
by Arthur Heymans (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Jincheng Li, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Shuo Liu. Arthur Heymans has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83330?usp=email ) Change subject: arch/x86: Decouple socket type from SoC type ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e15f26436626fbde7a93b47bea9f2601a302ffe Gerrit-Change-Number: 83330 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 03 Jul 2024 11:35:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: lib/smbios: Create SMBIOS type 4 entry
by Arthur Heymans (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Jincheng Li, Lean Sheng Tan, Patrick Rudolph, Shuo Liu. Arthur Heymans has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83331?usp=email ) Change subject: lib/smbios: Create SMBIOS type 4 entry ...................................................................... Patch Set 1: (1 comment) File src/lib/smbios.c: https://review.coreboot.org/c/coreboot/+/83331/comment/f52e57de_983e27db?us… : PS1, Line 446: nsigned int __weak smbios_get_max_socket(void) : { : return 1; : } How about the following, without the weak function: if (CONFIG_MAX_SOCKET == 1) return 1; else return soc_get_num_socket(); Maybe you need to define that Kconfig MAX_SOCKET in some place else with default 1, but I think this approach is cleaner. -- To view, visit https://review.coreboot.org/c/coreboot/+/83331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37 Gerrit-Change-Number: 83331 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 03 Jul 2024 11:34:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info
by Felix Singer (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Arthur Heymans, Jincheng Li, Lean Sheng Tan, Patrick Rudolph, Shuo Liu. Felix Singer has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83327?usp=email ) Change subject: mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info ...................................................................... Patch Set 1: (2 comments) File src/mainboard/intel/beechnutcity_crb/Kconfig: https://review.coreboot.org/c/coreboot/+/83327/comment/3a27d903_1eebb2ea?us… : PS1, Line 29: config MAINBOARD_VENDOR : string : default "Intel Corporation" Not needed. The vendor is configured in the Kconfig from mainboard/intel. https://review.coreboot.org/c/coreboot/+/83327/comment/8f014d62_41721835?us… : PS1, Line 37: config MAINBOARD_SERIAL_NUMBER : string : d Seems superfluous too. A dummy serial number is configured in the top-level Kconfig at src/Kconfig. -- To view, visit https://review.coreboot.org/c/coreboot/+/83327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a7d4958171df121e2cd3acb3a71554c695d64ab Gerrit-Change-Number: 83327 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 03 Jul 2024 11:27:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Add smbios_get_max_socket
by Shuo Liu (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83332?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Add smbios_get_max_socket ...................................................................... soc/intel/xeon_sp: Add smbios_get_max_socket TEST=Boot on intel/avenuecity CRB SMBIOS type 4 and type 7 entries are created according to CPU counts on multiple cpu platforms Change-Id: I10a20cf94821d4b6fa7af2637969724be1e3bf3d Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/util.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/83332/1 diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 4dbe7a4..9009666 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -11,6 +11,7 @@ #include <intelblocks/cpulib.h> #include <intelblocks/p2sb.h> #include <intelpch/lockdown.h> +#include <smbios.h> #include <soc/chip_common.h> #include <soc/pch_pci_devs.h> #include <soc/pci_devs.h> @@ -90,6 +91,11 @@ return get_iio_uds()->SystemStatus.numCpus; } +unsigned int smbios_get_max_socket(void) +{ + return soc_get_num_cpus(); +} + union p2sb_bdf soc_get_hpet_bdf(void) { if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/83332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10a20cf94821d4b6fa7af2637969724be1e3bf3d Gerrit-Change-Number: 83332 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: lib/smbios: Create SMBIOS type 4 entry
by Shuo Liu (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Jincheng Li. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83331?usp=email to review the following change. Change subject: lib/smbios: Create SMBIOS type 4 entry ...................................................................... lib/smbios: Create SMBIOS type 4 entry One smbios type 4 should be provided for each CPU instance. Create SMBIOS type 4 entry according to socket number, with a default value of 1. TEST=Boot on intel/archercity CRB No changes in boot log and 'dmidecode' result under centos Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/include/smbios.h M src/lib/smbios.c 2 files changed, 11 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/83331/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 8ef37d8..ec776b1 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -74,6 +74,7 @@ unsigned int smbios_cpu_get_max_speed_mhz(void); unsigned int smbios_cpu_get_current_speed_mhz(void); unsigned int smbios_cpu_get_voltage(void); +unsigned int smbios_get_max_socket(void); const char *smbios_mainboard_manufacturer(void); const char *smbios_mainboard_product_name(void); diff --git a/src/lib/smbios.c b/src/lib/smbios.c index ca71e3b..76d999f 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -443,6 +443,11 @@ return 0; /* Unknown */ } +unsigned int __weak smbios_get_max_socket(void) +{ + return 1; +} + static int smbios_write_type1(unsigned long *current, int handle) { struct smbios_type1 *t = smbios_carve_table(*current, SMBIOS_SYSTEM_INFORMATION, @@ -1233,9 +1238,11 @@ handle++; update_max(len, max_struct_size, smbios_write_type3(&current, handle++)); - struct smbios_type4 *type4 = (struct smbios_type4 *)current; - update_max(len, max_struct_size, smbios_write_type4(&current, handle++)); - len += smbios_write_type7_cache_parameters(&current, &handle, &max_struct_size, type4); + for (unsigned int s = 0; s < smbios_get_max_socket(); s++) { + struct smbios_type4 *type4 = (struct smbios_type4 *)current; + update_max(len, max_struct_size, smbios_write_type4(&current, handle++)); + len += smbios_write_type7_cache_parameters(&current, &handle, &max_struct_size, type4); + } update_max(len, max_struct_size, smbios_write_type11(&current, &handle)); if (CONFIG(ELOG)) update_max(len, max_struct_size, -- To view, visit https://review.coreboot.org/c/coreboot/+/83331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37 Gerrit-Change-Number: 83331 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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[S] Change in coreboot[main]: arch/x86: Decouple socket type from SoC type
by Shuo Liu (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Jincheng Li, Jérémy Compostella. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83330?usp=email to review the following change. Change subject: arch/x86: Decouple socket type from SoC type ...................................................................... arch/x86: Decouple socket type from SoC type Change-Id: I2e15f26436626fbde7a93b47bea9f2601a302ffe Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/arch/x86/smbios.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/83330/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 4fa8612..97d5f24 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -52,16 +52,16 @@ return PROCESSOR_UPGRADE_SOCKET_MPGA604; if (CONFIG(CPU_INTEL_SOCKET_LGA775)) return PROCESSOR_UPGRADE_SOCKET_LGA775; - if (CONFIG(SOC_INTEL_ALDERLAKE)) + if (CONFIG(CPU_INTEL_SOCKET_LGA1700)) return PROCESSOR_UPGRADE_SOCKET_LGA1700; - if (CONFIG(SOC_INTEL_METEORLAKE)) - return PROCESSOR_UPGRADE_OTHER; - if (CONFIG(SOC_INTEL_SKYLAKE_SP)) - return PROCESSOR_UPGRADE_SOCKET_LGA3647_1; - if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) + if (CONFIG(CPU_INTEL_SOCKET_LGA4189)) return PROCESSOR_UPGRADE_SOCKET_LGA4189; - if (CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP)) + if (CONFIG(CPU_INTEL_SOCKET_LGA4677)) return PROCESSOR_UPGRADE_SOCKET_LGA4677; + if (CONFIG(CPU_INTEL_SOCKET_LGA3647_1)) + return PROCESSOR_UPGRADE_SOCKET_LGA3647_1; + if (CONFIG(CPU_INTEL_SOCKET_OTHER)) + return PROCESSOR_UPGRADE_OTHER; return PROCESSOR_UPGRADE_UNKNOWN; } -- To view, visit https://review.coreboot.org/c/coreboot/+/83330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e15f26436626fbde7a93b47bea9f2601a302ffe Gerrit-Change-Number: 83330 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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[S] Change in coreboot[main]: cpu/intel: Add socket types
by Shuo Liu (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Jincheng Li, Johnny Lin, Morgan Jang. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83329?usp=email to review the following change. Change subject: cpu/intel: Add socket types ...................................................................... cpu/intel: Add socket types Add socket types for LGA1700, LGA3647_1, LGA4189, LGA4677. Select the socket type for different boards. For the socket types which are not defined in SMBIOS type4, CPU_INTEL_SOCKET_OTHER could be used. Change-Id: Ida3315694f3ce397b9ad9d676d3195da5f096cb7 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.mk A src/cpu/intel/socket_LGA1700/Kconfig A src/cpu/intel/socket_LGA3647_1/Kconfig A src/cpu/intel/socket_LGA4189/Kconfig A src/cpu/intel/socket_LGA4677/Kconfig A src/cpu/intel/socket_OTHER/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/archercity_crb/Kconfig M src/mainboard/intel/cedarisland_crb/Kconfig M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/ocp/tiogapass/Kconfig 12 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/83329/1 diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 0bbaf02..f28bbdb 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -25,6 +25,11 @@ source "src/cpu/intel/socket_mPGA604/Kconfig" source "src/cpu/intel/socket_441/Kconfig" source "src/cpu/intel/socket_LGA775/Kconfig" +source "src/cpu/intel/socket_LGA1700/Kconfig" +source "src/cpu/intel/socket_LGA3647_1/Kconfig" +source "src/cpu/intel/socket_LGA4189/Kconfig" +source "src/cpu/intel/socket_LGA4677/Kconfig" +source "src/cpu/intel/socket_OTHER/Kconfig" # Architecture specific features source "src/cpu/intel/fit/Kconfig" source "src/cpu/intel/turbo/Kconfig" diff --git a/src/cpu/intel/Makefile.mk b/src/cpu/intel/Makefile.mk index bc8f537..77b4618 100644 --- a/src/cpu/intel/Makefile.mk +++ b/src/cpu/intel/Makefile.mk @@ -17,5 +17,10 @@ subdirs-$(CONFIG_CPU_INTEL_HASWELL) += haswell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1700) += socket_LGA1700 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA3647_1) += socket_LGA3647_1 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA4189) += socket_LGA4189 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA4677) += socket_LGA4677 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_OTHER) += socket_OTHER subdirs-y += common diff --git a/src/cpu/intel/socket_LGA1700/Kconfig b/src/cpu/intel/socket_LGA1700/Kconfig new file mode 100644 index 0000000..7597a74 --- /dev/null +++ b/src/cpu/intel/socket_LGA1700/Kconfig @@ -0,0 +1,2 @@ +config CPU_INTEL_SOCKET_LGA1700 + bool diff --git a/src/cpu/intel/socket_LGA3647_1/Kconfig b/src/cpu/intel/socket_LGA3647_1/Kconfig new file mode 100644 index 0000000..a4d3e59 --- /dev/null +++ b/src/cpu/intel/socket_LGA3647_1/Kconfig @@ -0,0 +1,2 @@ +config CPU_INTEL_SOCKET_LGA3647_1 + bool diff --git a/src/cpu/intel/socket_LGA4189/Kconfig b/src/cpu/intel/socket_LGA4189/Kconfig new file mode 100644 index 0000000..39b8be4 --- /dev/null +++ b/src/cpu/intel/socket_LGA4189/Kconfig @@ -0,0 +1,2 @@ +config CPU_INTEL_SOCKET_LGA4189 + bool diff --git a/src/cpu/intel/socket_LGA4677/Kconfig b/src/cpu/intel/socket_LGA4677/Kconfig new file mode 100644 index 0000000..321a0ab --- /dev/null +++ b/src/cpu/intel/socket_LGA4677/Kconfig @@ -0,0 +1,2 @@ +config CPU_INTEL_SOCKET_LGA4677 + bool diff --git a/src/cpu/intel/socket_OTHER/Kconfig b/src/cpu/intel/socket_OTHER/Kconfig new file mode 100644 index 0000000..b544af1 --- /dev/null +++ b/src/cpu/intel/socket_OTHER/Kconfig @@ -0,0 +1,2 @@ +config CPU_INTEL_SOCKET_OTHER + bool diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 5ee091b..0171ebc 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -3,6 +3,7 @@ config BOARD_INTEL_ADLRVP_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 + select CPU_INTEL_SOCKET_LGA1700 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_MAX98373 diff --git a/src/mainboard/intel/archercity_crb/Kconfig b/src/mainboard/intel/archercity_crb/Kconfig index 200fa49..4d864d1 100644 --- a/src/mainboard/intel/archercity_crb/Kconfig +++ b/src/mainboard/intel/archercity_crb/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 + select CPU_INTEL_SOCKET_LGA4677 select CONSOLE_OVERRIDE_LOGLEVEL select IPMI_KCS select IPMI_KCS_ROMSTAGE diff --git a/src/mainboard/intel/cedarisland_crb/Kconfig b/src/mainboard/intel/cedarisland_crb/Kconfig index 4e3a1cc..8006667 100644 --- a/src/mainboard/intel/cedarisland_crb/Kconfig +++ b/src/mainboard/intel/cedarisland_crb/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 + select CPU_INTEL_SOCKET_LGA4189 select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index bbff4aa..84ebade 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -3,6 +3,7 @@ config BOARD_INTEL_MTLRVP_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 + select CPU_INTEL_SOCKET_OTHER select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index cbfb5c8..f20940f 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 + select CPU_INTEL_SOCKET_LGA3647_1 select HAVE_ACPI_TABLES select IPMI_KCS select IPMI_KCS_ROMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/83329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida3315694f3ce397b9ad9d676d3195da5f096cb7 Gerrit-Change-Number: 83329 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com>

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[M] Change in coreboot[main]: mb/intel/avenuecity_crb: Update SMBIOS type 0,1,2,3 info
by Shuo Liu (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Jincheng Li. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83328?usp=email to review the following change. Change subject: mb/intel/avenuecity_crb: Update SMBIOS type 0,1,2,3 info ...................................................................... mb/intel/avenuecity_crb: Update SMBIOS type 0,1,2,3 info Update BIOS version and unset card bus plugin support. Update mainboard info, wake-up type and SKU number. Update mainboard asset tag and feature flags. Update mainboard enclosure type, chassis version, chassis serial number and chassis power cords. Change-Id: I8e68c057fefa1d408fb8d69fef066cb573c929a4 Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com> --- M src/mainboard/intel/avenuecity_crb/Kconfig M src/mainboard/intel/avenuecity_crb/ramstage.c 2 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/83328/1 diff --git a/src/mainboard/intel/avenuecity_crb/Kconfig b/src/mainboard/intel/avenuecity_crb/Kconfig index fff244e..5fc8207 100644 --- a/src/mainboard/intel/avenuecity_crb/Kconfig +++ b/src/mainboard/intel/avenuecity_crb/Kconfig @@ -22,10 +22,18 @@ string default "intel/avenuecity_crb" +config MAINBOARD_VENDOR + string + default "Intel Corporation" + config MAINBOARD_PART_NUMBER string default "Avenue City CRB" +config MAINBOARD_SERIAL_NUMBER + string + default "UNKNOWN" + config FMDFILE string default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" diff --git a/src/mainboard/intel/avenuecity_crb/ramstage.c b/src/mainboard/intel/avenuecity_crb/ramstage.c index 1db2568..e1876bd 100644 --- a/src/mainboard/intel/avenuecity_crb/ramstage.c +++ b/src/mainboard/intel/avenuecity_crb/ramstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <smbios.h> #include <soc/dimm_slot.h> #include <soc/ramstage.h> @@ -8,6 +9,51 @@ } +const char *smbios_mainboard_bios_version(void) +{ + return "UNKNOWN"; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +const char *smbios_system_sku(void) +{ + return "UNKNOWN"; +} + +const char *smbios_mainboard_asset_tag(void) +{ + return "UNKNOWN"; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_RACK_MOUNT_CHASSIS; +} + +const char *smbios_chassis_version(void) +{ + return "UNKNOWN"; +} + +const char *smbios_chassis_serial_number(void) +{ + return "UNKNOWN"; +} + +u8 smbios_chassis_power_cords(void) +{ + return 1; +} + void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) { int size; -- To view, visit https://review.coreboot.org/c/coreboot/+/83328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8e68c057fefa1d408fb8d69fef066cb573c929a4 Gerrit-Change-Number: 83328 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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[M] Change in coreboot[main]: mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info
by Shuo Liu (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Jincheng Li. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83327?usp=email to review the following change. Change subject: mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info ...................................................................... mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info Update BIOS version and unset card bus plugin support. Update mainboard info, wake-up type and SKU number. Update mainboard asset tag and feature flags. Update mainboard enclosure type, chassis version, chassis serial number and chassis power cords. Change-Id: I8a7d4958171df121e2cd3acb3a71554c695d64ab Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com> --- M src/mainboard/intel/beechnutcity_crb/Kconfig M src/mainboard/intel/beechnutcity_crb/ramstage.c 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/83327/1 diff --git a/src/mainboard/intel/beechnutcity_crb/Kconfig b/src/mainboard/intel/beechnutcity_crb/Kconfig index 3c2f02a..ff0a98a 100644 --- a/src/mainboard/intel/beechnutcity_crb/Kconfig +++ b/src/mainboard/intel/beechnutcity_crb/Kconfig @@ -18,14 +18,26 @@ bool default n +config CARDBUS_PLUGIN_SUPPORT + bool + default n + config MAINBOARD_DIR string default "intel/beechnutcity_crb" +config MAINBOARD_VENDOR + string + default "Intel Corporation" + config MAINBOARD_PART_NUMBER string default "Beechnut City CRB" +config MAINBOARD_SERIAL_NUMBER + string + default "UNKNOWN" + config FMDFILE string default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" diff --git a/src/mainboard/intel/beechnutcity_crb/ramstage.c b/src/mainboard/intel/beechnutcity_crb/ramstage.c index 1db2568..e1876bd 100644 --- a/src/mainboard/intel/beechnutcity_crb/ramstage.c +++ b/src/mainboard/intel/beechnutcity_crb/ramstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <smbios.h> #include <soc/dimm_slot.h> #include <soc/ramstage.h> @@ -8,6 +9,51 @@ } +const char *smbios_mainboard_bios_version(void) +{ + return "UNKNOWN"; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +const char *smbios_system_sku(void) +{ + return "UNKNOWN"; +} + +const char *smbios_mainboard_asset_tag(void) +{ + return "UNKNOWN"; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_RACK_MOUNT_CHASSIS; +} + +const char *smbios_chassis_version(void) +{ + return "UNKNOWN"; +} + +const char *smbios_chassis_serial_number(void) +{ + return "UNKNOWN"; +} + +u8 smbios_chassis_power_cords(void) +{ + return 1; +} + void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) { int size; -- To view, visit https://review.coreboot.org/c/coreboot/+/83327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a7d4958171df121e2cd3acb3a71554c695d64ab Gerrit-Change-Number: 83327 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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