Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83680?usp=email )
Change subject: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE for Brox
......................................................................
soc/intel/adl: Update DCACHE_BSP_STACK_SIZE for Brox
During the stages which use Cache-as-RAM (CAR), Coreboot needs more than
1 KiB as configured in DCACHE_BSP_STACK_SIZE. Hence update that config
for Brox. For other boards, since it is part of RO update it on need
basis.
BUG=None
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/83680/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 470dbf4..298572b 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -191,12 +191,12 @@
config DCACHE_BSP_STACK_SIZE
hex
+ default 0x88000 if BOARD_GOOGLE_BROX_COMMON
default 0x80400
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be
- sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
- (~1KiB).
+ sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement.
config FSP_TEMP_RAM_SIZE
hex
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Change subject: soc/intel/meteorlake: Use ASPM helpers from Alder Lake
......................................................................
Set Ready For Review
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 26: Code-Review+2
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Change subject: mb/google/brox: Create jubilant variant
......................................................................
Patch Set 14:
(1 comment)
File src/mainboard/google/brox/variants/jubilant/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83212/comment/ef892bbe_c0085d00?us… :
PS14, Line 414: FP_MCU
FPMCU and not FP_MCU. This is the reason for the current Jenkins failure.
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Change subject: intel/alderlake: Add helper functions for Power Management
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Patch Set 26: Code-Review+2
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Change subject: mb/google/brya/var/orisa: Remove redundant defaults from overridetree
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83674/comment/8af6f2db_3814644f?us… :
PS4, Line 10: already exist in either the SoC-level or the platform-level configurations.
> `Possible unwrapped commit description (prefer a maximum 72 chars per line)`
Please fix.
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 25: Code-Review+1
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
intel/alderlake: Add helper functions for Power Management
Clock Power Management, ASPM and L1 Substates have been
configured the same way since Skylake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.
Despite the UPDs remaining the same since Skylake, this is not the
case for Alder Lake, Raptor Lake and Meteor Lake.
Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.
On Comet Lake, this results in the correct configuration, verified
with the lspci command:
```
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On Raptor Lake:
```
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```
Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.
Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.
Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 88 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81638/26
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Change subject: device/path: rename domain path struct element to 'domain_id'
......................................................................
Patch Set 2: Code-Review+2
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Change subject: device: introduce and use dev_get_domain_id
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