coreboot-gerrit July 2024

coreboot-gerrit@coreboot.org

1 participants
3025 discussions

[S] Change in coreboot[main]: device/path: rename domain path struct element to 'domain_id'
by Felix Held (Code Review) 29 Jul '24

29 Jul '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, Shuo Liu, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83677?usp=email to look at the new patch set (#2). Change subject: device/path: rename domain path struct element to 'domain_id' ...................................................................... device/path: rename domain path struct element to 'domain_id' Rename the 'domain' element of the 'domain_path' struct to 'domain_id' to clarify that this element is the domain ID. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7 --- M src/device/device_const.c M src/device/device_util.c M src/include/device/path.h M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/spr/ioat.c M util/sconfig/main.c 6 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/83677/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7 Gerrit-Change-Number: 83677 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

1 0

[S] Change in coreboot[main]: device/path: rename domain path struct element to 'domain_id'
by Felix Held (Code Review) 29 Jul '24

29 Jul '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, Shuo Liu, Tim Chu. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83677?usp=email ) Change subject: device/path: rename domain path struct element to 'domain_id' ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/xeon_sp/include/soc/chip_common.h: https://review.coreboot.org/c/coreboot/+/83677/comment/bb39f5c3_26d18a15?us… : PS1, Line 33: domain_path that isn't really the domain path, but the domain id, but i wasn't sure if i should change that and even if so that would be something for a follow-up. would be good if an Intel engineer could have a look at that one -- To view, visit https://review.coreboot.org/c/coreboot/+/83677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7 Gerrit-Change-Number: 83677 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Jul 2024 15:29:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: intel/alderlake: Add helper functions for Power Management
by Sean Rhodes (Code Review) 29 Jul '24

29 Jul '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eric Lai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Nico Huber, Paul Menzel, Sean Rhodes, Subrata Banik. Hello Angel Pons, Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Nico Huber, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81638?usp=email to look at the new patch set (#25). Change subject: intel/alderlake: Add helper functions for Power Management ...................................................................... intel/alderlake: Add helper functions for Power Management Clock Power Management, ASPM and L1 Substates have been configured the same way since Skylake. The main control to enable or disable is Kconfig, and then the level can be overridden in devicetree. Despite the UPDs remaining the same since Skylake, this is not the case for Alder Lake, Raptor Lake and Meteor Lake. Taking `starlabs/starbook` as an example, at the time of this commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE enabled. On Comet Lake, this results in the correct configuration, verified with the lspci command: ``` LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- ``` On Raptor Lake: ``` LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+ ``` Clock Power Management, ASPM and L1 Substates are also not configured for CPU root ports. Add helper functions to configure these correctly based on Kconfig, but retain the capability to override the specific levels from devicetree. Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 2 files changed, 88 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81638/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/81638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81 Gerrit-Change-Number: 81638 Gerrit-PatchSet: 25 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

1 0

[S] Change in coreboot[main]: device: introduce and use dev_get_domain_id
by Felix Held (Code Review) 29 Jul '24

29 Jul '24

Attention is currently required from: Arthur Heymans, Christian Walter, Fred Reitberger, Jason Glenesk, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Patrick Rudolph, Shuo Liu, Tim Chu, Varshit Pandya. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83644?usp=email ) Change subject: device: introduce and use dev_get_domain_id ...................................................................... Patch Set 3: (1 comment) This change is ready for review. File src/device/device_util.c: https://review.coreboot.org/c/coreboot/+/83644/comment/f1e1e171_d84246e1?us… : PS1, Line 269: die("%s: doesn't have a domain device\n", dev_path(dev)); > it seems extremely unlikely that we'd fail to find the domain - with the current callers. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288 Gerrit-Change-Number: 83644 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Jul 2024 15:27:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[S] Change in coreboot[main]: device/path: rename domain path struct element to 'domain_id'
by Felix Held (Code Review) 29 Jul '24

29 Jul '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83677?usp=email ) Change subject: device/path: rename domain path struct element to 'domain_id' ...................................................................... device/path: rename domain path struct element to 'domain_id' Rename the 'domain' element of the 'domain_path' struct to 'domain_id' to clarify that this element is the domain ID. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7 --- M src/device/device_const.c M src/device/device_util.c M src/include/device/path.h M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/spr/ioat.c M util/sconfig/main.c 6 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/83677/1 diff --git a/src/device/device_const.c b/src/device/device_const.c index fc76304..9f3443e 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -118,7 +118,7 @@ equal = (path1->apic.apic_id == path2->apic.apic_id); break; case DEVICE_PATH_DOMAIN: - equal = (path1->domain.domain == path2->domain.domain); + equal = (path1->domain.domain_id == path2->domain.domain_id); break; case DEVICE_PATH_CPU_CLUSTER: equal = (path1->cpu_cluster.cluster diff --git a/src/device/device_util.c b/src/device/device_util.c index a8fe06f..ee96062 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -108,7 +108,7 @@ ret |= dev->path.apic.apic_id; break; case DEVICE_PATH_DOMAIN: - ret |= dev->path.domain.domain; + ret |= dev->path.domain.domain_id; break; case DEVICE_PATH_CPU_CLUSTER: ret |= dev->path.cpu_cluster.cluster; @@ -192,7 +192,7 @@ break; case DEVICE_PATH_DOMAIN: snprintf(buffer, sizeof(buffer), "DOMAIN: %08x", - dev->path.domain.domain); + dev->path.domain.domain_id); break; case DEVICE_PATH_CPU_CLUSTER: snprintf(buffer, sizeof(buffer), "CPU_CLUSTER: %01x", @@ -270,12 +270,12 @@ return 0; } - return domain_dev->path.domain.domain; + return domain_dev->path.domain.domain_id; } bool is_domain0(const struct device *dev) { - return dev && dev->path.type == DEVICE_PATH_DOMAIN && dev->path.domain.domain == 0; + return dev && dev->path.type == DEVICE_PATH_DOMAIN && dev->path.domain.domain_id == 0; } bool is_dev_on_domain0(const struct device *dev) diff --git a/src/include/device/path.h b/src/include/device/path.h index f8c4390..d8ef880 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -53,7 +53,7 @@ } struct domain_path { - unsigned int domain; + unsigned int domain_id; }; struct pci_path { diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 4731bec..ed278a3 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -30,7 +30,7 @@ .bus = bus, }; path->type = DEVICE_PATH_DOMAIN; - path->domain.domain = dp.domain_path; + path->domain.domain_id = dp.domain_path; }; /* diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 8b9921a..fcc3a20 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -44,7 +44,7 @@ struct device_path path = { .type = DEVICE_PATH_DOMAIN, .domain = { - .domain = new_path.domain_path, + .domain_id = new_path.domain_path, }, }; struct device *const domain = alloc_find_dev(upstream, &path); diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 9acd592..acab06a 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -859,7 +859,7 @@ break; case DOMAIN: - new_d->path = ".type=DEVICE_PATH_DOMAIN,{.domain={ .domain = 0x%x }}"; + new_d->path = ".type=DEVICE_PATH_DOMAIN,{.domain={ .domain_id = 0x%x }}"; break; case GENERIC: -- To view, visit https://review.coreboot.org/c/coreboot/+/83677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7 Gerrit-Change-Number: 83677 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[S] Change in coreboot[main]: soc/intel/alderlake: Hook up PCI Power Management to option API
by Dinesh Gehlot (Code Review) 29 Jul '24

29 Jul '24

Attention is currently required from: Kapil Porwal, Nick Vaccaro, Sean Rhodes, Subrata Banik. Dinesh Gehlot has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/81906?usp=email ) Change subject: soc/intel/alderlake: Hook up PCI Power Management to option API ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/81906/comment/ff751556_0295fb54?us… : PS8, Line 496: pciexp_aspm It seems redundant execution of `get_uint_option()`. The parent routine `configure_cpu_rp_power_management() `has already obtained and shared the value of `pciexp_aspm`. -- To view, visit https://review.coreboot.org/c/coreboot/+/81906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956 Gerrit-Change-Number: 81906 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 29 Jul 2024 15:17:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: mb/google/brya/var/orisa: Remove redundant defaults from overridetree
by Dinesh Gehlot (Code Review) 29 Jul '24

29 Jul '24

Attention is currently required from: Amanda Hwang, Kapil Porwal, Nick Vaccaro, Rishika Raj. Dinesh Gehlot has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83674?usp=email ) Change subject: mb/google/brya/var/orisa: Remove redundant defaults from overridetree ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83674?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e Gerrit-Change-Number: 83674 Gerrit-PatchSet: 3 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Jul 2024 15:07:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: MAINTAINERS: Update email id for ADL and google/brya mbs
by Dinesh Gehlot (Code Review) 29 Jul '24

29 Jul '24

Attention is currently required from: Jayvik Desai, Pranava Y N, Rishika Raj. Dinesh Gehlot has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83675?usp=email ) Change subject: MAINTAINERS: Update email id for ADL and google/brya mbs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83675?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idcdd3e2525b621310aaf43608fd5fede8133d16a Gerrit-Change-Number: 83675 Gerrit-PatchSet: 1 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 29 Jul 2024 15:06:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK comment
by Felix Held (Code Review) 29 Jul '24

29 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83649?usp=email ) Change subject: soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK comment ...................................................................... soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK comment The comment for the BOOTBLOCK region should be written right above the BOOTBLOCK declaration. BUG=b:317009620 TEST=none BRANCH=none Change-Id: I7afdf74844a9d97169b4e4a23c3c9c6060e886d9 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83649 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/include/soc/memlayout.ld 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index e0975c7..664e55b 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -40,8 +40,8 @@ * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz */ DRAM_INIT_CODE(0x02000000, 600K) - /* 4K reserved for BOOTROM until BOOTBLOCK is started */ #else + /* The beginning 4K of SRAM_L2C is reserved for BOOTROM until BOOTBLOCK is started. */ BOOTBLOCK(0x02001000, 60K) #endif OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K) -- To view, visit https://review.coreboot.org/c/coreboot/+/83649?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7afdf74844a9d97169b4e4a23c3c9c6060e886d9 Gerrit-Change-Number: 83649 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: mb/google/nissa: Create teliks variant
by Qinghong Zeng (Code Review) 29 Jul '24

29 Jul '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Weimin Wu. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Weimin Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83408?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/nissa: Create teliks variant ...................................................................... mb/google/nissa: Create teliks variant Create the teliks variant of the nissa reference board by copying the anraggar files to a new directory named for the variant. BUG=b:352263941 BRANCH=None TEST=1. util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TELIKS 2. Run part_id_gen tool without any errors Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768 Signed-off-by: zengqinghong <zengqinghong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/teliks/Makefile.mk A src/mainboard/google/brya/variants/teliks/data.vbt A src/mainboard/google/brya/variants/teliks/gpio.c A src/mainboard/google/brya/variants/teliks/include/variant/ec.h A src/mainboard/google/brya/variants/teliks/include/variant/gpio.h A src/mainboard/google/brya/variants/teliks/memory/Makefile.mk A src/mainboard/google/brya/variants/teliks/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/teliks/overridetree.cb A src/mainboard/google/brya/variants/teliks/variant.c 12 files changed, 856 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/83408/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/83408?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768 Gerrit-Change-Number: 83408 Gerrit-PatchSet: 14 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2024