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Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> > Okay, but shouldn't they be the stock ones then? And then Google has a "custom" directory or somet […]
Fair enough. The problem with the header Kconfig is the memory info hobs differ in the Intel downloads; there's a Kconfig tied to that but it seems to break other things so the only way is to smush the directories together.
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Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Okay, but shouldn't they be the stock ones then? And then Google has a "custom" directory or something like that for their version?
I just had a conversation with Felix about this issue. You are right that it would be better if Google could have their own directory for their FSP headers. The problem is that Google was the only company engaging with Intel during the pre-silicon to PRQ stage of SoC, so no one else needed to interact with the headers. However, it’s definitely possible to override the FSP header path (kconfig) with another directory if you want.
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Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> > These are quite different to the ones in the download from R&D; are they specific to google or som […]
Okay, but shouldn't they be the stock ones then? And then Google has a "custom" directory or something like that for their version?
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Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> These are quite different to the ones in the download from R&D; are they specific to google or something like that?
We might have added few more FSP UPD on top of the FSP official release to meet the CrOS boot requirement.
Also, this header is known as partial header because Intel at times not okay to open the complete FSP header (during pre-prq phase)
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Change subject: mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/protectli/vault_adl_p/bootblock.c:
https://review.coreboot.org/c/coreboot/+/80501/comment/6f8b18c4_d6aa9d47?us… :
PS7, Line 41: polarity << pin
> This looks rather odd. I think it says we'd only clear it if we are going to […]
I will look into ITE datasheets I have at hand and see how much can be shared. Definitely not all chips have the same number of sets and number of GPIOs in each set.
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Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
These are quite different to the ones in the download from R&D; are they specific to google or something like that?
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Change subject: mb/intel/avenuecity_crb: Update SMBIOS type 0,1,2,3 info
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/intel/avenuecity_crb/Kconfig:
https://review.coreboot.org/c/coreboot/+/83328/comment/7a07bbe0_b263d4c9?us… :
PS1, Line 27: default "Intel Corporation"
Seems superfluous. Mainboard vendor is configured in the upper Kconfig file.
https://review.coreboot.org/c/coreboot/+/83328/comment/2cd19141_492743f2?us… :
PS1, Line 33: config MAINBOARD_SERIAL_NUMBER
: string
: default "UNKNOWN"
Same. A dummy serial number is configured in the top-level Kconfig at src/Kconfig.
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Change subject: mb/intel/avenuecity_crb: Update SMBIOS type 0,1,2,3 info
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Patch Set 1: Code-Review+2
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