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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83354?usp=email
to look at the new patch set (#23).
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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,265 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/23
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Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/82252/comment/037ec8c2_6d0eba3c?us… :
PS6, Line 192: PCI_SECONDARY_BUS
are there root ports that do not act as a bridge and thus have PCI_SECONDARY_BUS==0?
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Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/82252/comment/d84a6988_83576f2d?us… :
PS4, Line 194: acpigen_write_BBN
> Hi Patrick, in patch set 5, I removed the _BBN generation for PCI root port for alignment for UEFI i […]
Done
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Change subject: mb/google/nissa: Create teliks variant
......................................................................
Patch Set 16:
(1 comment)
File src/mainboard/google/brya/variants/teliks/data.vbt:
PS16:
> Can we refer to Karthik's comment?
can you please share the link ? sorry unable t find the comment that you are referring
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Change subject: src: Include new gbb flag to enforce cse sync
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83685/comment/0bc31794_01dcc3a7?us… :
PS1, Line 12:
> > to make sure this is test only GBB
>
> I think all the GBB flags are for testing or development purposes. Real users should not be able to modify GBB flags without unlocking RO. Therefore maybe no need to highlight that in this particular flag?
I am a little hesitant to proceed because FAFT GBB has been used by users to implement various workarounds in coreboot, depthcharge, and other areas. As a result, I want to be sure that we clearly state that this is only for testing the CSE sync feature and should not be used to implement any other workarounds.
File src/security/vboot/Kconfig:
https://review.coreboot.org/c/coreboot/+/83685/comment/7d4d09ee_24d12b91?us… :
PS1, Line 454: CSME
> I actually don't know the difference between CSE and CSME (and ME). I remember Reka said in somewhere that they are the same thing. Is that not correct?
CS (converged security) + ME (manageability engine) = CSME
We often use the CSE part alone because ME part is dependent of the use case like enterprise etc.
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Change subject: payloads/external/edk2: configure capsule updates
......................................................................
Patch Set 1:
(1 comment)
File payloads/external/edk2/Makefile:
https://review.coreboot.org/c/coreboot/+/83682/comment/6a62e09d_db0b181c?us… :
PS1, Line 151: ifneq ($(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES),)
This is inside `ifeq ($(CONFIG_EDK2_REPO_MRCHROMEBOX),y)`, shouldn't this be part of upstream edk2 or at least common options instead?
Possibly related to discussion in CB:82721
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Change subject: Makefile.mk: Remove linker warning on RWX segments
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> > This breaks building with binutils < 2.39. […]
We have xcompile for such cases: CB:83693
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Change subject: [UNTESTED] Makefile: Move `--no-warn-rwx-segments' into xcompile
......................................................................
[UNTESTED] Makefile: Move `--no-warn-rwx-segments' into xcompile
Change-Id: I02982769ae2c356f037a747e85d155368bfcb730
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M Makefile.mk
M util/xcompile/xcompile
2 files changed, 6 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/83693/1
diff --git a/Makefile.mk b/Makefile.mk
index e9ad2cc..901d6b2 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -604,9 +604,6 @@
LDFLAGS_common += --nmagic
LDFLAGS_common += -static
LDFLAGS_common += -z noexecstack
-# Disable warning on segments with RWX.
-# All loadable sections are placed in the same segment for simplicity.
-LDFLAGS_common += --no-warn-rwx-segments
# Workaround for RISC-V linker bug, merge back into above line when fixed.
# https://sourceware.org/bugzilla/show_bug.cgi?id=27180
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index b3012b5..4c5285f 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -208,6 +208,12 @@
testcc "$GCC" "$CFLAGS_GCC -Wcalloc-transposed-args" &&
CFLAGS_GCC="$CFLAGS_GCC -Wcalloc-transposed-args"
+ # Disable warning on segments with RWX.
+ # All loadable sections are placed in the same segment for simplicity.
+ testld "$GCC" "$FLAGS_GCC" "${GCCPREFIX}ld${LINKER_SUFFIX}" \
+ "$LDFLAGS --no-warn-rwx-segments" && \
+ LDFLAGS="$LDFLAGS --no-warn-rwx-segments"
+
case "$architecture" in
x86)
;;
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