Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83695?usp=email )
Change subject: mb/google/trulo: Keep ISH default enable
......................................................................
mb/google/trulo: Keep ISH default enable
This patch drops fw_config probing for ISH because ISH IP should
remains on by default for all Trulo variants.
Additionally, removed the redundant ISH entries from variant
override devicetree.
BUG=b:354607924
TEST=Able to verify ISH PCI Device is available while booting eMMC sku.
```
lspci
00:00.0 Host bridge: Intel Corporation Device 461c
...
00:12.0 Serial controller: Intel Corporation Device 54fc
...
00:1a.0 SD Host controller: Intel Corporation Device 54c4
```
Also, able to enter S0ix with this patch.
```
> suspend_stress_test -c 1 --ignore_s0ix_substates
At AP console:
s0ix errors: 0
s0ix substate errors: 0
s0ix pc10 errors: 0
At EC console:
power state 5 = S0ix, in 0x38d87
```
Change-Id: Ic1e415ec848ac91a9bbf21b26597f4e6b5f7a1f5
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
M src/mainboard/google/brya/variants/orisa/overridetree.cb
M src/mainboard/google/brya/variants/trulo/overridetree.cb
3 files changed, 6 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/83695/1
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
index f048dbb..8e1093a 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
@@ -45,6 +45,12 @@
device ref igpu on end
device ref dtt on end
device ref tcss_xhci on end
+ device ref ish on
+ chip drivers/intel/ish
+ register "add_acpi_dma_property" = "true"
+ device generic 0 on end
+ end
+ end
device ref xhci on end
device ref shared_sram on end
device ref heci1 on end
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb
index 92909ab..0a58b3d 100644
--- a/src/mainboard/google/brya/variants/orisa/overridetree.cb
+++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb
@@ -512,14 +512,6 @@
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_EMMC
end
- device ref ish on
- chip drivers/intel/ish
- register "add_acpi_dma_property" = "true"
- device generic 0 on end
- end
- probe STORAGE STORAGE_UNKNOWN
- probe STORAGE STORAGE_UFS
- end
device ref ufs on
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_UFS
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index 3ae9f85..d7fca12 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -518,14 +518,6 @@
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_EMMC
end
- device ref ish on
- chip drivers/intel/ish
- register "add_acpi_dma_property" = "true"
- device generic 0 on end
- end
- probe STORAGE STORAGE_UNKNOWN
- probe STORAGE STORAGE_UFS
- end
device ref ufs on
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_UFS
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Sergii Dmytruk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83682?usp=email )
Change subject: payloads/external/edk2: configure capsule updates
......................................................................
Patch Set 1:
(1 comment)
File payloads/external/edk2/Makefile:
https://review.coreboot.org/c/coreboot/+/83682/comment/3b6df79f_50d1883e?us… :
PS1, Line 151: ifneq ($(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES),)
> This is inside `ifeq ($(CONFIG_EDK2_REPO_MRCHROMEBOX),y)`, shouldn't this be part of upstream edk2 o […]
Thanks, that wasn't intentional.
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Verified+1 by build bot (Jenkins)
Change subject: payloads/external/edk2: configure capsule updates
......................................................................
payloads/external/edk2: configure capsule updates
This requires version of EDK2 in use to understand those defines, but
the build isn't affected negatively if they aren't handled. Upstream
EDK2 doesn't understand them at the moment but should in the future.
Change-Id: I1c684cb8929842a5d3c4b06e8a9c0a748470ea41
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M payloads/external/Makefile.mk
M payloads/external/edk2/Makefile
2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/83682/2
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,270 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/29
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Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/82252/comment/aaf72eb0_bcb14c94?us… :
PS6, Line 192: PCI_SECONDARY_BUS
> there are no for SPR/GNR.
I checked the SPR log, the empty but enabled root port will also be assigned with secondary bus numbers by coreboot/OS.
```
[DEBUG] DOMAIN: 00000337 scanning...
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 37
[SPEW ] PCI: 00:37:00.0 [8086/0000] ops
[DEBUG] PCI: 00:37:00.0 [8086/09a2] enabled
[DEBUG] PCI: 00:37:00.1 [8086/09a4] enabled
[DEBUG] PCI: 00:37:00.2 [8086/09a3] enabled
[DEBUG] PCI: 00:37:00.3 [8086/09a5] enabled
[SPEW ] PCI: 00:37:00.4 [8086/0000] ops
[DEBUG] PCI: 00:37:00.4 [8086/0b23] enabled
[DEBUG] PCI: 00:37:01.0 subordinate bus PCI Express
[DEBUG] PCI: 00:37:01.0 [8086/352a] enabled
[DEBUG] PCI: 00:37:01.0 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:37:01.0
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 38
[INFO ] PCI: 00:37:01.0: Setting Max_Payload_Size to 512 for devices under this root port
[DEBUG] scan_bus: bus PCI: 00:37:01.0 finished in 19 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000337 finished in 74 msecs
```
```
ACPI: PCI Root Bridge [PC03] (domain 0000 [bus 37-47])
acpi PNP0A08:03: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
acpi PNP0A08:03: PCIe port services disabled; not requesting _OSC control
PCI host bridge to bus 0000:37
pci_bus 0000:37: root bus resource [io 0x7000-0x7fff window]
pci_bus 0000:37: root bus resource [mem 0xa9400000-0xb2ffffff window]
pci_bus 0000:37: root bus resource [mem 0x203000000000-0x203fffffffff window]
pci_bus 0000:37: root bus resource [bus 37-47]
pci 0000:37:00.0: [8086:09a2] type 00 class 0x088000
pci 0000:37:00.1: [8086:09a4] type 00 class 0x088000
pci 0000:37:00.2: [8086:09a3] type 00 class 0x088000
pci 0000:37:00.3: [8086:09a5] type 00 class 0x088000
pci 0000:37:00.4: [8086:0b23] type 00 class 0x080700
pci 0000:37:01.0: [8086:352a] type 01 class 0x060400
pci 0000:37:01.0: reg 0x10: [mem 0x203ffffe0000-0x203fffffffff 64bit]
pci 0000:37:01.0: enabling Extended Tags
pci 0000:37:01.0: PME# supported from D0 D3hot D3cold
pci 0000:37:01.0: PCI bridge to [bus 38]
```
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,270 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/28
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