Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83697?usp=email )
Change subject: MAINTAINERS: Add Maximilian Brune to RISC-V
......................................................................
MAINTAINERS: Add Maximilian Brune to RISC-V
I also add myself as the Maintainer for the SiFive boards, since I
happen to have both of them and I also ported the HiFive Unmatched to
coreboot.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Ic0b8e1053c9f5007e29e997c1ff21ff4a496aea8
---
M MAINTAINERS
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/83697/1
diff --git a/MAINTAINERS b/MAINTAINERS
index 2c7b6e6..0fc18e9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -597,7 +597,8 @@
SIFIVE MAINBOARDS
-S: Orphan
+M: Maximilian Brune <maximilian.brune(a)9elements.com>
+S: Maintained
F: src/mainboard/sifive/
@@ -658,6 +659,7 @@
RISC-V ARCHITECTURE
M: Ronald Minnich <rminnich(a)gmail.com>
+M: Maximilian Brune <maximilian.brune(a)9elements.com>
R: Philipp Hug <philipp(a)hug.cx>
S: Maintained
F: src/arch/riscv/
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Bob Moragues has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/83212?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/brox: Create jubilant variant
......................................................................
Patch Set 16:
(3 comments)
File src/mainboard/google/brox/variants/jubilant/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83212/comment/74ba7824_5ba841e5?us… :
PS16, Line 11: 11 12
Move this after ISH to be bits 14 15
https://review.coreboot.org/c/coreboot/+/83212/comment/e7f662ce_8b26841a?us… :
PS16, Line 15: 17 18
This should probably match the FP field in config.star (bits 11 12)
https://review.coreboot.org/c/coreboot/+/83212/comment/f2483c40_e8b9e614?us… :
PS16, Line 1: fw_config
: field STORAGE 2 3
: option STORAGE_UNKNOWN 0
: option STORAGE_UFS 1
: option STORAGE_NVME 2
: end
: field WIFI_BT 4 4
: option WIFI_BT_CNVI 0
: option WIFI_BT_PCIE 1
: end
: field DB_USB 11 12
: option DB_1A 0
: option DB_1A_LTE 1
: end
: field FPMCU 17 18
: option FPMCU_ABSENT 0
: option FPMCU_NUVOTON 1
: end
: end
This needs to match the config,star bits here:
http://cs/h/chrome-internal/chromeos/superproject/+/main:src/project/brox/l…
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Change subject: mb/google/nissa: Create teliks variant
......................................................................
Patch Set 18:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/83408/comment/2bf21b8c_b5584b73?us… :
PS17, Line 540: select INTEL_GMA_HAVE_VBT
> Hi Subrata,
>
> Yes, it seems to be the cause. After removing it, I compiled it locally and it passed. Thanks.
yes, while building the coreboot in chromium tree, this won't be an issue because config.baseboard.nissa would select RUN_FSP_GOP and that would internally again select INTEL_GMA_HAVE_VBT.
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Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83671?usp=email )
Change subject: mb/google/trulo: support ISH
......................................................................
Set Ready For Review
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Change subject: mb/google/nissa: Create teliks variant
......................................................................
Patch Set 18:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/83408/comment/9eee07f4_c6f093e9?us… :
PS17, Line 540: select INTEL_GMA_HAVE_VBT
> can you please drop this Kconfig and give it a try?
Hi Subrata,
Yes, it seems to be the cause. After removing it, I compiled it locally and it passed. Thanks.
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Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Weimin Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83408?usp=email
to look at the new patch set (#18).
Change subject: mb/google/nissa: Create teliks variant
......................................................................
mb/google/nissa: Create teliks variant
Create the teliks variant of the nissa reference board by copying
the anraggar files to a new directory named for the variant.
BUG=b:352263941
BRANCH=None
TEST=1. util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TELIKS
2. Run part_id_gen tool without any errors
Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768
Signed-off-by: zengqinghong <zengqinghong(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/teliks/Makefile.mk
A src/mainboard/google/brya/variants/teliks/gpio.c
A src/mainboard/google/brya/variants/teliks/include/variant/ec.h
A src/mainboard/google/brya/variants/teliks/include/variant/gpio.h
A src/mainboard/google/brya/variants/teliks/memory/Makefile.mk
A src/mainboard/google/brya/variants/teliks/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/teliks/overridetree.cb
A src/mainboard/google/brya/variants/teliks/variant.c
11 files changed, 827 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/83408/18
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Change subject: mb/google/nissa: Create teliks variant
......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/83408/comment/858e913d_3585bcc8?us… :
PS17, Line 540: select INTEL_GMA_HAVE_VBT
can you please drop this Kconfig and give it a try?
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Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83696?usp=email )
Change subject: mb/system76/mtl: darp10: Add TCSS configs
......................................................................
mb/system76/mtl: darp10: Add TCSS configs
Fixes using USB3 devices at USB3 speeds in all ports.
Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/mainboard/system76/mtl/variants/darp10/overridetree.cb
M src/mainboard/system76/mtl/variants/darp10/ramstage.c
2 files changed, 27 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83696/1
diff --git a/src/mainboard/system76/mtl/variants/darp10/overridetree.cb b/src/mainboard/system76/mtl/variants/darp10/overridetree.cb
index 5648739..8baa556 100644
--- a/src/mainboard/system76/mtl/variants/darp10/overridetree.cb
+++ b/src/mainboard/system76/mtl/variants/darp10/overridetree.cb
@@ -5,7 +5,26 @@
subsystemid 0x1558 0xa743 inherit
device ref tbt_pcie_rp0 on end
- device ref tcss_xhci on end
+ device ref tcss_xhci on
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+ register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+ # TCP2 is used as HDMI
+ # TCP3 is not used
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""TBT Type-C""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device ref tcss_usb3_port0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB Type-C""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device ref tcss_usb3_port1 on end
+ end
+ end
+ end
+ end
device ref tcss_dma0 on end
device ref xhci on
register "usb2_ports" = "{
diff --git a/src/mainboard/system76/mtl/variants/darp10/ramstage.c b/src/mainboard/system76/mtl/variants/darp10/ramstage.c
index 2762794..63dfb35 100644
--- a/src/mainboard/system76/mtl/variants/darp10/ramstage.c
+++ b/src/mainboard/system76/mtl/variants/darp10/ramstage.c
@@ -4,6 +4,13 @@
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
+ // Enable TCP1 USB-A conversion
+ // BIT 0:3 is mapping to PCH XHCI USB2 port
+ // BIT 4:5 is reserved
+ // BIT 6 is orientational
+ // BIT 7 is enable
+ params->EnableTcssCovTypeA[1] = 0x82;
+
// XXX: Enabling C10 reporting causes system to constantly enter and
// exit opportunistic suspend when idle.
params->PchEspiHostC10ReportEnable = 0;
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