Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun.
Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,270 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/29
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Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82252?usp=email )
Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/82252/comment/aaf72eb0_bcb14c94?us… :
PS6, Line 192: PCI_SECONDARY_BUS
> there are no for SPR/GNR.
I checked the SPR log, the empty but enabled root port will also be assigned with secondary bus numbers by coreboot/OS.
```
[DEBUG] DOMAIN: 00000337 scanning...
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 37
[SPEW ] PCI: 00:37:00.0 [8086/0000] ops
[DEBUG] PCI: 00:37:00.0 [8086/09a2] enabled
[DEBUG] PCI: 00:37:00.1 [8086/09a4] enabled
[DEBUG] PCI: 00:37:00.2 [8086/09a3] enabled
[DEBUG] PCI: 00:37:00.3 [8086/09a5] enabled
[SPEW ] PCI: 00:37:00.4 [8086/0000] ops
[DEBUG] PCI: 00:37:00.4 [8086/0b23] enabled
[DEBUG] PCI: 00:37:01.0 subordinate bus PCI Express
[DEBUG] PCI: 00:37:01.0 [8086/352a] enabled
[DEBUG] PCI: 00:37:01.0 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:37:01.0
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 38
[INFO ] PCI: 00:37:01.0: Setting Max_Payload_Size to 512 for devices under this root port
[DEBUG] scan_bus: bus PCI: 00:37:01.0 finished in 19 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000337 finished in 74 msecs
```
```
ACPI: PCI Root Bridge [PC03] (domain 0000 [bus 37-47])
acpi PNP0A08:03: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
acpi PNP0A08:03: PCIe port services disabled; not requesting _OSC control
PCI host bridge to bus 0000:37
pci_bus 0000:37: root bus resource [io 0x7000-0x7fff window]
pci_bus 0000:37: root bus resource [mem 0xa9400000-0xb2ffffff window]
pci_bus 0000:37: root bus resource [mem 0x203000000000-0x203fffffffff window]
pci_bus 0000:37: root bus resource [bus 37-47]
pci 0000:37:00.0: [8086:09a2] type 00 class 0x088000
pci 0000:37:00.1: [8086:09a4] type 00 class 0x088000
pci 0000:37:00.2: [8086:09a3] type 00 class 0x088000
pci 0000:37:00.3: [8086:09a5] type 00 class 0x088000
pci 0000:37:00.4: [8086:0b23] type 00 class 0x080700
pci 0000:37:01.0: [8086:352a] type 01 class 0x060400
pci 0000:37:01.0: reg 0x10: [mem 0x203ffffe0000-0x203fffffffff 64bit]
pci 0000:37:01.0: enabling Extended Tags
pci 0000:37:01.0: PME# supported from D0 D3hot D3cold
pci 0000:37:01.0: PCI bridge to [bus 38]
```
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Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun.
Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83354?usp=email
to look at the new patch set (#28).
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,270 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/28
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,270 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/27
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,271 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/26
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Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82252?usp=email )
Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
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Patch Set 6:
(1 comment)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/82252/comment/6b34206c_231dad6b?us… :
PS6, Line 192: PCI_SECONDARY_BUS
> are there root ports that do not act as a bridge and thus have PCI_SECONDARY_BUS==0?
there are no for SPR/GNR.
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