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Change subject: nb/via/cx700: Implement PCI function disablement
......................................................................
Patch Set 1:
(1 comment)
File src/northbridge/via/cx700/chip.c:
https://review.coreboot.org/c/coreboot/+/83390/comment/a149897d_d4f623e5?us… :
PS1, Line 9: #define DISABLE_MC97_BIT 7
What is MC97? Judging from the WWW it’s the modem controller. Maybe mention a datasheet in the commit message?
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Change subject: libpayload/commonlib: warning fixes
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> We want to go ahead and enable more of the `-Wextra` warnings anyway. […]
Splitting up the commit into smaller commits would be much appreciated.
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Change subject: nb/via/cx700: Implement PCI function disablement
......................................................................
Patch Set 1:
(1 comment)
File src/northbridge/via/cx700/chip.c:
https://review.coreboot.org/c/coreboot/+/83390/comment/2037c409_d68cfd12?us… :
PS1, Line 36: dev->enabled || _dev_uhci1_ptr->enabled ||
> nit: why is this a tab? […]
Heh, probably because I re-arranged the lines when adding the comment.
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Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83396?usp=email )
Change subject: soc/intel/meteorlake: Conditional selection of CSE Lite PSR
......................................................................
soc/intel/meteorlake: Conditional selection of CSE Lite PSR
This patch makes the selection of `SOC_INTEL_CSE_LITE_PSR` conditional
on both `MAINBOARD_HAS_CHROMEOS` and `SOC_INTEL_CSE_LITE_SKU` being
enabled.
This ensures that CSE Lite PSR is only active when both ChromeOS is the
target platform and CSE sync is performed inside coreboot.
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I7199c034bbe6e7f077650417da67fa544f0b49d5
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83396/1
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 622d35f..5ec891f 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -91,7 +91,7 @@
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_IOC
select SOC_INTEL_CRASHLOG
- select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS
+ select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS && SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_CSE_SET_EOP
select SOC_INTEL_IOE_DIE_SUPPORT
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Change subject: soc/intel: Extend CSE RW Update and ME read access for payload sync
......................................................................
soc/intel: Extend CSE RW Update and ME read access for payload sync
Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and
`ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include
`SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`.
This allows these features to be enabled even when CSE sync is performed
in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU`
config is enabled).
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/block/cse/Kconfig
M src/southbridge/intel/common/firmware/Kconfig
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/83395/1
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index d8d2456..c4aa6b5 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -184,7 +184,7 @@
config SOC_INTEL_CSE_RW_UPDATE
bool "Enable the CSE RW Update Feature"
default n
- depends on SOC_INTEL_CSE_LITE_SKU
+ depends on SOC_INTEL_CSE_LITE_SKU || SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
help
This config will enable CSE RW firmware update feature and also will be used ensure
all the required configs are provided by mainboard.
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig
index 45d8be8..95eda31 100644
--- a/src/southbridge/intel/common/firmware/Kconfig
+++ b/src/southbridge/intel/common/firmware/Kconfig
@@ -67,7 +67,7 @@
config ME_REGION_ALLOW_CPU_READ_ACCESS
bool "Allows HOST/CPU read access to ME region"
depends on HAVE_IFD_BIN
- default y if SOC_INTEL_CSE_LITE_SKU
+ default y if SOC_INTEL_CSE_LITE_SKU || SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
default n
help
The config ensures Host has read access to the ME region if it is locked
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