coreboot-gerrit July 2024

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[XS] Change in coreboot[main]: soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds
by Matt DeVillier (Code Review) 09 Jul '24

09 Jul '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83401?usp=email ) Change subject: soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds ...................................................................... soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds The APOB NV size/base are embedded into the amdfw binary and read by the PSP, and need to be synchronized with the FMAP region used by coreboot to store the APOB data. soc_update_apob_cache() will only use RECOVERY_MRC_CACHE if supported if vboot is enabled, so the NV base passed to the PSP needs to reflect that as well. This fixes the issue of RAM training running on every boot on non-vboot builds for Myst boards. TEST=untested, but same change as made for Mendocino Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/amd/phoenix/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/83401/1 diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index be0a022..03edd43 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -130,7 +130,7 @@ APOB_NV_BASE=$(call _tohex,$(call int-subtract, \ $(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) $(FMAP_FLASH_START))) -ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) +ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE)$(CONFIG_VBOOT),yy) # On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. # Else use RW_MRC_CACHE. This entry will be added in the RO section. APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) -- To view, visit https://review.coreboot.org/c/coreboot/+/83401?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35 Gerrit-Change-Number: 83401 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds
by Matt DeVillier (Code Review) 09 Jul '24

09 Jul '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83400?usp=email ) Change subject: soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds ...................................................................... soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds The APOB NV size/base are embedded into the amdfw binary and read by the PSP, and need to be synchronized with the FMAP region used by coreboot to store the APOB data. soc_update_apob_cache() will only use RECOVERY_MRC_CACHE if supported if vboot is enabled, so the NV base passed to the PSP needs to reflect that as well. This fixes the issue of RAM training running on every boot on non-vboot builds for Skyrim boards. TEST=build/boot Skyrim (Frostflow), verify RAM training only run on first boot after flashing. Change-Id: I9be1699d675331b46ee9c42570700c2b72588025 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/amd/mendocino/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/83400/1 diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk index a72116e..1b96ff1 100644 --- a/src/soc/amd/mendocino/Makefile.mk +++ b/src/soc/amd/mendocino/Makefile.mk @@ -122,7 +122,7 @@ APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) -ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) +ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE)$(CONFIG_VBOOT),yy) # On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. # Else use RW_MRC_CACHE. This entry will be added in the RO section. APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) -- To view, visit https://review.coreboot.org/c/coreboot/+/83400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9be1699d675331b46ee9c42570700c2b72588025 Gerrit-Change-Number: 83400 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: nb/via/cx700: Implement PCI function disablement
by Nico Huber (Code Review) 09 Jul '24

09 Jul '24

Attention is currently required from: Angel Pons, Paul Menzel. Nico Huber has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/83390?usp=email ) Change subject: nb/via/cx700: Implement PCI function disablement ...................................................................... Patch Set 1: (1 comment) File src/northbridge/via/cx700/chip.c: https://review.coreboot.org/c/coreboot/+/83390/comment/ecf48478_2b98915d?us… : PS1, Line 9: #define DISABLE_MC97_BIT 7 > What is MC97? Judging from the WWW it’s the modem controller. […] That's it. This particular bit is not documented, though. I'll add links to CB:82765. -- To view, visit https://review.coreboot.org/c/coreboot/+/83390?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97ac61bca336465ce64e1c2b57d40e7ddd7f2643 Gerrit-Change-Number: 83390 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Jul 2024 21:49:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: via: Start template for VIA C7 w/ CX700 northbridge
by Nico Huber (Code Review) 09 Jul '24

09 Jul '24

Nico Huber has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/82765?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: via: Start template for VIA C7 w/ CX700 northbridge ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82765/comment/ad1486d6_90e6374a?us… : PS2, Line 19: Add links: DS: https://theretroweb.com/chip/documentation/via-cx700-datasheet-feb06-666c8b… PM: https://web.archive.org/web/20180616220857/http://linux.via.com.tw/support/… -- To view, visit https://review.coreboot.org/c/coreboot/+/82765?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574 Gerrit-Change-Number: 82765 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Jul 2024 21:47:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: ec/google/chromeec: Stop checking CBI for UCSI
by Karthik Ramasubramanian (Code Review) 09 Jul '24

09 Jul '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83252?usp=email ) Change subject: ec/google/chromeec: Stop checking CBI for UCSI ...................................................................... ec/google/chromeec: Stop checking CBI for UCSI The ucsi_enabled flag is no longer used by the EC. Update coreboot to only use only EC_FEATURE_UCSI_PPM to determine whether UCSI is enabled. BUG=b:319124515 TEST=emerge-brox coreboot chromeos-bootimage Cq-Depend: chromium:5664227 Change-Id: Ia9d820c637e56a527fd90f45b1848158a960dee7 Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83252 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Reviewed-by: Forest Mittelberg <bmbm(a)google.com> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/ec.c 1 file changed, 1 insertion(+), 13 deletions(-) Approvals: Forest Mittelberg: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Caveh Jalali: Looks good to me, approved Daisuke Nojiri: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index a32b2a5..088f2fe 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -726,7 +726,6 @@ bool google_chromeec_get_ucsi_enabled(void) { int rv; - union ec_common_control cc; rv = google_chromeec_check_feature(EC_FEATURE_UCSI_PPM); if (rv < 0) { @@ -734,18 +733,7 @@ return false; } - if (rv == 0) - return false; - - /* Check if PPM is enabled at runtime. */ - cc.ucsi_enabled = 0; - rv = cbi_get_uint32(&cc.raw_value, CBI_TAG_COMMON_CONTROL); - if (rv < 0) { - printk(BIOS_DEBUG, "Cannot get tag CBI_TAG_COMMON_CONTROL from CBI: status = %d\n", rv); - return false; - } - - return (cc.ucsi_enabled != 0); + return rv != 0; } static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag) -- To view, visit https://review.coreboot.org/c/coreboot/+/83252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9d820c637e56a527fd90f45b1848158a960dee7 Gerrit-Change-Number: 83252 Gerrit-PatchSet: 4 Gerrit-Owner: Abhishek Pandit-Subedi <abhishekpandit(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Short <keithshort(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: tree: Change set_msip(int, int) to set_msip(uintptr_t, int)
by Elyes Haouas (Code Review) 09 Jul '24

09 Jul '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83399?usp=email ) Change subject: tree: Change set_msip(int, int) to set_msip(uintptr_t, int) ...................................................................... tree: Change set_msip(int, int) to set_msip(uintptr_t, int) Change-Id: I23a10d5ac276817b9c533e74d7f309a26193d2ee Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/riscv/include/mcall.h M src/arch/riscv/sbi.c M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/clint.c M src/soc/sifive/fu540/clint.c M src/soc/sifive/fu740/clint.c 6 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/83399/1 diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index c6ed7d8..3d57f46 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -78,7 +78,7 @@ * a bit, a byte, a word, and so on. * So we can't provide code that is related to implementation. */ -void set_msip(int hartid, int val); +void set_msip(uintptr_t hartid, int val); #endif // __ASSEMBLER__ diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index 2ef7625..ca287da 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -12,7 +12,7 @@ static uintptr_t send_ipi(uintptr_t *pmask, intptr_t type) { uintptr_t mask = mprv_read_uintptr_t(pmask); - for (int i = 0; mask; i++) { + for (uintptr_t i = 0; mask; i++) { if (mask & 1) { OTHER_HLS(i)->ipi_pending |= type; /* send soft interrupt to target hart */ diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index 10827fa..f755254 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -12,7 +12,7 @@ HLS()->timecmp = (uint64_t *)(QEMU_VIRT_CLINT + 0x4000 + 8 * hart_id); } -void set_msip(int hartid, int val) +void set_msip(uintptr_t hartid, int val) { - write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); + write32((void *)(QEMU_VIRT_CLINT + 4 * hartid), !!val); } diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 4d45bce..db13b32 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -13,7 +13,7 @@ HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id); } -void set_msip(int hartid, int val) +void set_msip(uintptr_t hartid, int val) { - write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); + write32((void *)(SPIKE_CLINT_BASE + 4 * hartid), !!val); } diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c index 08124d3..4366aa8 100644 --- a/src/soc/sifive/fu540/clint.c +++ b/src/soc/sifive/fu540/clint.c @@ -12,7 +12,7 @@ HLS()->timecmp = (uint64_t *)(FU540_CLINT + 0x4000 + 8 * hart_id); } -void set_msip(int hartid, int val) +void set_msip(uintptr_t hartid, int val) { - write32((void *)(FU540_CLINT + 4 * (uintptr_t)hartid), !!val); + write32((void *)(FU540_CLINT + 4 * hartid), !!val); } diff --git a/src/soc/sifive/fu740/clint.c b/src/soc/sifive/fu740/clint.c index 818b628..cba0176 100644 --- a/src/soc/sifive/fu740/clint.c +++ b/src/soc/sifive/fu740/clint.c @@ -15,7 +15,7 @@ HLS()->timecmp = (uint64_t *)(FU740_CLINT + CLINT_MTIMECMP + 8 * hart_id); } -void set_msip(int hartid, int val) +void set_msip(uintptr_t hartid, int val) { - write32((void *)(FU740_CLINT + 4 * (uintptr_t)hartid), !!val); + write32((void *)(FU740_CLINT + 4 * hartid), !!val); } -- To view, visit https://review.coreboot.org/c/coreboot/+/83399?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23a10d5ac276817b9c533e74d7f309a26193d2ee Gerrit-Change-Number: 83399 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: releases/coreboot-24.08: Remove ACPICA line
by Elyes Haouas (Code Review) 09 Jul '24

09 Jul '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83384?usp=email ) Change subject: releases/coreboot-24.08: Remove ACPICA line ...................................................................... releases/coreboot-24.08: Remove ACPICA line ACPICA reverted from 20240321 to 20230628 (commit 7c1813c1). Change-Id: Id238f77c6a0b4052ae3d835caf98aaf26a7e570f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83384 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M Documentation/releases/coreboot-24.08-relnotes.md 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Nico Huber: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/releases/coreboot-24.08-relnotes.md b/Documentation/releases/coreboot-24.08-relnotes.md index 6873b0e..b509b2a 100644 --- a/Documentation/releases/coreboot-24.08-relnotes.md +++ b/Documentation/releases/coreboot-24.08-relnotes.md @@ -40,7 +40,6 @@ ### Toolchain updates -* Upgrade ACPICA from 20230628 to 20240321 * Upgrade CMake from 3.28.3 to 3.29.3 * Upgrade nasm from 2.16.01 to 2.16.03 * Upgrade LLVM from 17.0.6 to 18.1.6 -- To view, visit https://review.coreboot.org/c/coreboot/+/83384?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id238f77c6a0b4052ae3d835caf98aaf26a7e570f Gerrit-Change-Number: 83384 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Documentation/Makefile: Fix test target
by Elyes Haouas (Code Review) 09 Jul '24

09 Jul '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83381?usp=email ) Change subject: Documentation/Makefile: Fix test target ...................................................................... Documentation/Makefile: Fix test target The test target called make with the `-K` flag, which is not valid. Change it to `-k` (keep going if some targets fail) which is what was probably intended. It also tried to build the `doctest` target from Makefile.sphinx, which results in an error. Further investigation reveals that this is because the sphinx doctest extension was not enabled in conf.py. However, from the documentation of doctest [1], it seems like it is intended to ensure that documentation containing Python snippets along with the expected output of the snippet remain in sync, which is something that we probably don't need. So, remove the call to it. [1] https://www.sphinx-doc.org/en/master/usage/extensions/doctest.html" Change-Id: Id514950b4486ed8644d078af222c96ed711fc8f9 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83381 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Documentation/Makefile 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: Nico Huber: Looks good to me, approved Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/Makefile b/Documentation/Makefile index ec1e1a4..6d2a641 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -31,8 +31,7 @@ test: @echo "Test for logging purposes - Failing tests will not fail the build" - -$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx html - -$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx doctest + -$(MAKE) -f Makefile.sphinx clean && $(MAKE) -k -f Makefile.sphinx html help: @echo "all - Builds all documentation targets" -- To view, visit https://review.coreboot.org/c/coreboot/+/83381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id514950b4486ed8644d078af222c96ed711fc8f9 Gerrit-Change-Number: 83381 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: Documentation: Fix header levels
by Elyes Haouas (Code Review) 09 Jul '24

09 Jul '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83382?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Documentation: Fix header levels ...................................................................... Documentation: Fix header levels This fixes the following MyST Parser warnings: - Non-consecutive header level increase - Document headings start at H2, not H1 The header levels (the number of "#" characters before a heading) are intended to form a logical hierarchy of each section and subsection in a document. A subsection typically should have a header level one more than its parent section. Most of these warnings are caused by extra "#" characters, which were simply removed, or sections missing a "#" character to make it fall under its parent section. Notable changes: getting_started/kconfig.md: Changed the header level of the "Keywords" section from 2 to 3 to fall under "Kconfig Language" (level 2), and increased the level of each keyword from 3 to 4 to remain under "Keywords". This also fixes the warnings of "H3 to H5" increases, since the Usage/Example/Notes/Restrictions sections for each keyword had a level of 5. soc/intel/cse_fw_update/cse_fw_update.md: Changed the first line to a top level header acting as the title of the document. Without this soc/intel/index.md displays all the level 2 headers in this document instead of a single link to cse_fw_update.md. Change-Id: Ia1f8b52e39b7b6524bef89a95365541235b5b1b9 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83382 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Documentation/getting_started/kconfig.md M Documentation/mainboard/lenovo/montevina_series.md M Documentation/mainboard/starlabs/common/building.md M Documentation/mainboard/starlabs/common/flashing.md M Documentation/releases/coreboot-24.02-relnotes.md M Documentation/releases/coreboot-4.21-relnotes.md M Documentation/releases/coreboot-4.22-relnotes.md M Documentation/soc/intel/cse_fw_update/cse_fw_update.md M Documentation/tutorial/part1.md M Documentation/util/abuild/index.md M Documentation/util/intelp2m/index.md 11 files changed, 65 insertions(+), 66 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Elyes Haouas: Looks good to me, approved diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index c9e9b3c..bff077c 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -200,9 +200,9 @@ visible in the front end. -## Keywords +### Keywords -### bool +#### bool The 'bool' keyword assigns a boolean type to a symbol. The allowable values for a boolean type are 'n' or 'y'. The keyword can be followed by an optional prompt @@ -238,7 +238,7 @@ -------------------------------------------------------------------------------- -### choice +#### choice This creates a selection list of one or more boolean symbols. For bools, only one of the symbols can be selected, and one will be be forced to be selected, @@ -301,7 +301,7 @@ -------------------------------------------------------------------------------- -### comment +#### comment This keyword defines a line of text that is displayed to the user in the configuration frontend and is additionally written to the output files. @@ -326,7 +326,7 @@ -------------------------------------------------------------------------------- -### config +#### config This is the keyword that starts a block defining a Kconfig symbol. The symbol modifiers follow the 'config' statement. @@ -363,7 +363,7 @@ -------------------------------------------------------------------------------- -### default +#### default The ‘default’ keyword assigns a value to a symbol in the case where no preset value exists, i.e. the symbol is not present and assigned in .config. If there @@ -403,7 +403,7 @@ -------------------------------------------------------------------------------- -### def_bool +#### def_bool ‘def_bool’ is similar to the 'bool' keyword in that it sets a symbol’s type to boolean. It lets you set the type and default value at the same time, instead @@ -437,7 +437,7 @@ -------------------------------------------------------------------------------- -### depends on +#### depends on This defines a dependency for a menu entry, including symbols and comments. It behaves the same as surrounding the menu entry with an if/endif block. If the @@ -466,28 +466,28 @@ -------------------------------------------------------------------------------- -### endchoice +#### endchoice This ends a choice block. See the 'choice' keyword for more information and an example. -------------------------------------------------------------------------------- -### endif +#### endif This ends a block started by the 'if' keyword. See the 'if' keyword for more information and an example. -------------------------------------------------------------------------------- -### endmenu +#### endmenu This ends a menu block. See the 'menu' keyword for more information and an example. -------------------------------------------------------------------------------- -### help +#### help The 'help' keyword defines the subsequent block of text as help for a config or choice block. The help block is started by the 'help' keyword on a line by @@ -519,7 +519,7 @@ -------------------------------------------------------------------------------- -### hex +#### hex This is another symbol type specifier, specifying an unsigned integer value formatted as hexadecimal. @@ -555,7 +555,7 @@ -------------------------------------------------------------------------------- -### if +#### if The 'if' keyword is overloaded, used in two different ways. The first definition enables and disables various other keywords, and follows the other keyword @@ -596,7 +596,7 @@ -------------------------------------------------------------------------------- -### int +#### int A type setting keyword, defines a symbol as an integer, accepting only signed numeric values. The values can be further restricted with the ‘range’ keyword. @@ -632,7 +632,7 @@ -------------------------------------------------------------------------------- -### mainmenu +#### mainmenu The 'mainmenu' keyword sets the title or title bar of the configuration front end, depending on how the configuration program decides to use it. It can only @@ -652,7 +652,7 @@ -------------------------------------------------------------------------------- -### menu +#### menu The 'menu' and 'endmenu' keywords tell the configuration front end that the enclosed statements are part of a group of related pieces. @@ -699,7 +699,7 @@ -------------------------------------------------------------------------------- -### prompt +#### prompt The 'prompt' keyword sets the text displayed for a config symbol or choice in configuration front end. @@ -752,7 +752,7 @@ prompt "Prompt value 2" -------------------------------------------------------------------------------- -### range +#### range This sets the allowable minimum and maximum entries for hex or int type config symbols. @@ -774,7 +774,7 @@ -------------------------------------------------------------------------------- -### select +#### select The ‘select’ keyword is used within a bool type config block. In coreboot (and other projects that don't use modules), the 'select' keyword can force an @@ -818,7 +818,7 @@ -------------------------------------------------------------------------------- -### source +#### source The 'source' keyword functions much the same as an 'include' statement in c. This pulls one or more files into Kconfig at the location of the 'source' @@ -877,7 +877,7 @@ -------------------------------------------------------------------------------- -### string +#### string The last of the symbol type assignment keywords. 'string' allows a text value to be entered. @@ -923,7 +923,7 @@ -## Keywords not used in coreboot at the time of writing: +### Keywords not used in coreboot at the time of writing: - allnoconfig_y: - defconfig_list @@ -948,7 +948,7 @@ #define SYMBOL NAME XXX -##### Symbol types: +#### Symbol types: - bool, int, and hex types - Every symbol of one of these types created in the Kconfig tree is defined. It doesn’t matter whether they’re in an if/endif block, or have a ‘depends on’ statement - they ALL end up being defined in @@ -1168,19 +1168,19 @@ ## Kconfig Editor Highlighting -#### vim: +### vim: vim has syntax highlighting for Kconfig built in (or at least as a part of vim-common), but most editors do not. -#### ultraedit: +### ultraedit: https://github.com/martinlroth/wordfiles/blob/master/kconfig.uew -#### atom: +### atom: https://github.com/martinlroth/language-kconfig diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index e4e5da3..120a161 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -46,7 +46,7 @@ your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or [use one from the coreboot repository](#using-checked-in-flash-descriptor-via-bincfg). -#### Modifying flash descriptor using ifdtool +### Modifying flash descriptor using ifdtool Pick the layout according to your chip size from the table below and save it to the `new_layout.txt` file: @@ -88,7 +88,7 @@ Continue to the [Configuring coreboot](#configuring-coreboot) section. -#### Using checked-in flash descriptor via bincfg +### Using checked-in flash descriptor via bincfg There is a copy of an X200's flash descriptor checked into the coreboot repository. It is supposed to work for the T400/T500 as well. The descriptor @@ -119,7 +119,7 @@ It will be saved to the `flashregion_0_fd.bin` file. -#### Configuring coreboot +### Configuring coreboot Now configure coreboot. You need to select correct chip size and specify paths to flash descriptor and gbe dump. diff --git a/Documentation/mainboard/starlabs/common/building.md b/Documentation/mainboard/starlabs/common/building.md index 3b9b568..c283ef5 100644 --- a/Documentation/mainboard/starlabs/common/building.md +++ b/Documentation/mainboard/starlabs/common/building.md @@ -1,15 +1,15 @@ -## Building coreboot +# Building coreboot -### Preliminaries +## Preliminaries Prior to building coreboot the following files are required: -#### StarBook series: +### StarBook series: * Intel Flash Descriptor file (descriptor.bin) * Intel Management Engine firmware (me.bin) * ITE Embedded Controller firmware (ec.bin) -#### StarLite series: +### StarLite series: * Intel Flash Descriptor file (descriptor.bin) * IFWI Image (ifwi.rom) @@ -18,7 +18,7 @@ These files exist in the correct location in the [StarLabsLtd/blobs](https://github.com/StarLabsLtd/blobs) repo on GitHub which is used in place of the standard 3rdparty/blobs repo. -### Build +## Build The following commands will build a working image, where the last two words represent the series and processor i.e. `lite_glkr`: diff --git a/Documentation/mainboard/starlabs/common/flashing.md b/Documentation/mainboard/starlabs/common/flashing.md index c5764b9..46b98af 100644 --- a/Documentation/mainboard/starlabs/common/flashing.md +++ b/Documentation/mainboard/starlabs/common/flashing.md @@ -1,6 +1,6 @@ # Flashing with fwupd -#### **Requirements:** +## **Requirements:** * fwupd version 1.5.6 or later * The battery must be charged to at least 30% @@ -44,7 +44,7 @@ 4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm. -#### **Switching Branch** +## **Switching Branch** Switching branch refers to changing from AMI firmware to coreboot, or vice versa. diff --git a/Documentation/releases/coreboot-24.02-relnotes.md b/Documentation/releases/coreboot-24.02-relnotes.md index f82a6a8..4b98d57 100644 --- a/Documentation/releases/coreboot-24.02-relnotes.md +++ b/Documentation/releases/coreboot-24.02-relnotes.md @@ -12,7 +12,7 @@ The next release is scheduled for mid-May. -### Release number format update +## Release number format update The previous release was the last to use the incrementing 4.xx release name scheme. For this and future releases, coreboot has switched to a @@ -22,7 +22,7 @@ append the values .01, .02 and so on to the initial release value. -### The master branch is being deleted +## The master branch is being deleted The coreboot project changed from master to main roughly 6 months ago, and has been keeping the two branches in sync since then to ease the @@ -197,8 +197,7 @@ the version of verstage used in coreboot 24.02. -## Issues from the coreboot bugtracker: https://ticket.coreboot.org/ - +Issues from the coreboot bugtracker: https://ticket.coreboot.org/ ### coreboot-wide or architecture-wide issues diff --git a/Documentation/releases/coreboot-4.21-relnotes.md b/Documentation/releases/coreboot-4.21-relnotes.md index 5e493b5..05d334f 100644 --- a/Documentation/releases/coreboot-4.21-relnotes.md +++ b/Documentation/releases/coreboot-4.21-relnotes.md @@ -13,7 +13,7 @@ starting to use coreboot recently, and we appreciate all of the contributions and support. -### Upcoming switch from master branch to main branch +## Upcoming switch from master branch to main branch Historically, the initial branch that was created in a new git repository was named ‘master’. In line with many other projects, diff --git a/Documentation/releases/coreboot-4.22-relnotes.md b/Documentation/releases/coreboot-4.22-relnotes.md index a36bc81..8d0cc7a 100644 --- a/Documentation/releases/coreboot-4.22-relnotes.md +++ b/Documentation/releases/coreboot-4.22-relnotes.md @@ -11,7 +11,7 @@ security enhancements, and expanding hardware support. -### 4.22.01 release +## 4.22.01 release The week between tagging a release and announcing it publicly is used to test the tagged version and make sure everything is working as we @@ -22,7 +22,7 @@ the sandybridge/ivybridge platforms and rolled that into the 4.22.01 release package. -### coreboot version naming update +## coreboot version naming update This release is the last release to use the incrementing 4.xx release name scheme. For future releases, coreboot is switching to a @@ -33,7 +33,7 @@ initial release value. -### coreboot default branch update +## coreboot default branch update Immediately after the 4.21 release, the coreboot project changed the default git branch from 'master' to 'main'. For the first couple of diff --git a/Documentation/soc/intel/cse_fw_update/cse_fw_update.md b/Documentation/soc/intel/cse_fw_update/cse_fw_update.md index 54a5e61..ec797e2 100644 --- a/Documentation/soc/intel/cse_fw_update/cse_fw_update.md +++ b/Documentation/soc/intel/cse_fw_update/cse_fw_update.md @@ -1,4 +1,4 @@ -CSE FW update mechanism for devices in field +# CSE FW update mechanism for devices in field ## Introduction diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index bba00d5..88be6ff 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -86,7 +86,7 @@ ### Step 5 - Configure the build -##### Configure your mainboard +#### Configure your mainboard ```Bash make menuconfig @@ -104,7 +104,7 @@ These should be the default selections, so if anything else was set, run `make distclean` to remove your old config file and start over. -##### Optionally use your system toolchain (Again, not recommended) +#### Optionally use your system toolchain (Again, not recommended) ```Text select 'General Setup' menu @@ -112,7 +112,7 @@ select < Exit > ``` -##### Select the payload +#### Select the payload ```Text select 'Payload' menu @@ -125,7 +125,7 @@ select < Yes > ``` -##### Check your configuration (optional step): +#### Check your configuration (optional step): ```Bash make savedefconfig diff --git a/Documentation/util/abuild/index.md b/Documentation/util/abuild/index.md index 4def2f6..31a267e 100644 --- a/Documentation/util/abuild/index.md +++ b/Documentation/util/abuild/index.md @@ -14,7 +14,7 @@ Note that abuild is a tool to do a simple build test, and binaries it produces may well not boot if flashed to a system. -### Basic usage +## Basic usage abuild needs to be run from the coreboot directory. If you cd into the coreboot/util/abuild directory and try to run it from there, it will @@ -30,7 +30,7 @@ $ util/abuild/abuild -t lenovo/x230 ``` -### Where builds and logs are stored +## Where builds and logs are stored The resulting images and logs are stored in directory coreboot-builds/ under your current directory. This can be overridden with --outdir: @@ -53,7 +53,7 @@ **These logs are overwritten with each abuild run.** Save them elsewhere if you feel a need to reference the results later. -### Payloads +## Payloads You can also specify a payload directory with -p: @@ -81,7 +81,7 @@ util/abuild/abuild -t lenovo/x230 -p none ``` -### Build non-default configurations +## Build non-default configurations Sometimes you do need to build test a custom, non-default configuration. This can be accomplished by placing a config file in configs/. @@ -142,7 +142,7 @@ and run `abuild -K myconfig` to build everything with a silent postcar stage. -### Selectively build certain targets only (also config file naming caveats) +## Selectively build certain targets only (also config file naming caveats) The P8Z77-M PRO example above would fail for P8Z77-M, because the config file name is ambiguous. `abuild` would pick up this config when @@ -166,7 +166,7 @@ This example skips building configs not using (Sandy/Ivy Bridge) native RAM init. -### Additional Examples +## Additional Examples Many boards have multiple variants. You can build for a specific variant of a board: @@ -203,7 +203,7 @@ util/abuild/abuild -B -y -c 8 -p none ``` -### Full options list +## Full options list ```text coreboot autobuild v0.11.01 (Feb 3, 2023) diff --git a/Documentation/util/intelp2m/index.md b/Documentation/util/intelp2m/index.md index 6873c1b1..98b9c00 100644 --- a/Documentation/util/intelp2m/index.md +++ b/Documentation/util/intelp2m/index.md @@ -11,7 +11,7 @@ ./intelp2m -file /path/to/inteltool.log ``` -### Platforms +## Platforms It is possible to use templates for parsing inteltool.log files. To specify such a pattern, use the option `-t <template number>`. @@ -51,13 +51,13 @@ ./intelp2m -p <platform> -file path/to/inteltool.log ``` -### Packages +## Packages ![][pckgs] [pckgs]: gopackages.png -### Bit fields in macros +## Bit fields in macros Use the `-fld=cb` option to only generate a sequence of bit fields in a new macro: @@ -71,7 +71,7 @@ PAD_PULL(DN_20K)), /* LPSS_UART0_TXD */ ``` -### Raw DW0, DW1 register value +## Raw DW0, DW1 register value To generate the gpio.c with raw PAD_CFG_DW0 and PAD_CFG_DW1 register values you need to use the -fld=raw option: @@ -96,7 +96,7 @@ _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000), ``` -### Macro Check +## Macro Check After generating the macro, the utility checks all used fields of the configuration registers. If some field has been @@ -115,7 +115,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), ``` -### Information level +## Information level The utility can generate additional information about the bit fields of the DW0 and DW1 configuration registers. Using the @@ -158,7 +158,7 @@ DISPUPD), ``` -### Ignoring Fields +## Ignoring Fields Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields from it that are not in the corresponding PAD_CFG_*() macro: @@ -177,7 +177,7 @@ PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), ``` -### FSP-style macro +## FSP-style macro The utility allows one to generate macros that include fsp/edk2-platform style bitfields: @@ -205,6 +205,6 @@ GpioPadConfigLock }, ``` -### Supported Chipsets +## Supported Chipsets Sunrise PCH, Lewisburg PCH, Apollo Lake SoC, CannonLake-LP SoCs -- To view, visit https://review.coreboot.org/c/coreboot/+/83382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia1f8b52e39b7b6524bef89a95365541235b5b1b9 Gerrit-Change-Number: 83382 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: Docs: Fix paths in references to other markdown documents
by Elyes Haouas (Code Review) 09 Jul '24

09 Jul '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83383?usp=email ) Change subject: Docs: Fix paths in references to other markdown documents ...................................................................... Docs: Fix paths in references to other markdown documents This fixes a few "cross-reference target not found" warnings from MyST parser. In these cases, the relative path to the target markdown document was incorrect. Change-Id: I5d01deacc3ba7401faba30fc832e2357d4aedad8 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83383 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M Documentation/mainboard/dell/e7240.md M Documentation/mainboard/prodrive/hermes.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md 3 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/Documentation/mainboard/dell/e7240.md b/Documentation/mainboard/dell/e7240.md index 2188ee5..8a9090a 100644 --- a/Documentation/mainboard/dell/e7240.md +++ b/Documentation/mainboard/dell/e7240.md @@ -80,4 +80,4 @@ [Dell Latitude E7240]: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… [dell-flash-unlock]: https://github.com/nic3-14159/dell-flash-unlock -[flashing tutorial]: ../../flash_tutorial/ext_power.md +[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md diff --git a/Documentation/mainboard/prodrive/hermes.md b/Documentation/mainboard/prodrive/hermes.md index 726382c..db86130 100644 --- a/Documentation/mainboard/prodrive/hermes.md +++ b/Documentation/mainboard/prodrive/hermes.md @@ -49,6 +49,6 @@ ## Extra links [flashrom]: https://flashrom.org/Flashrom -[flashing tutorial]: ../../../../tutorial/flashing_firmware/ext_power.md -[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md +[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md +[Intel FSP2.0]: ../../soc/intel/fsp/index.md [AST2500]: https://www.aspeedtech.com/products.php?fPath=20&rId=440 diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md index 206f7f9..91a0985 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -61,6 +61,6 @@ [Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151 [OpenBMC]: https://www.openbmc.org/ [flashrom]: https://flashrom.org/Flashrom -[flashing tutorial]: ../../../../tutorial/flashing_firmware/ext_power.md -[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md +[flashing tutorial]: ../../../tutorial/flashing_firmware/ext_power.md +[Intel FSP2.0]: ../../../soc/intel/fsp/index.md [AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 -- To view, visit https://review.coreboot.org/c/coreboot/+/83383?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d01deacc3ba7401faba30fc832e2357d4aedad8 Gerrit-Change-Number: 83383 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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