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Change subject: xcompile: Use CLANG_CFLAGS_${TARCH} option per line
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83374/comment/d521d9c9_40a241cc?us… :
PS1, Line 7: xcompile: Use CLANG_CFLAGS_${TARCH} option per line
How about
```
xcompile: Use one line per CLANG_CFLAGS_${TARCH} flag
```
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Change subject: payloads/external/iPXE/Makefile: Build iPXE for EFI target if requested
......................................................................
Patch Set 1:
(1 comment)
File payloads/external/iPXE/Makefile:
https://review.coreboot.org/c/coreboot/+/83385/comment/2fd08240_9cb574e9?us… :
PS1, Line 14: ifeq ($(CONFIG_IPXE_BUILD_EFI),y)
I think you forgot to add a Kconfig option to your commit.
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Change subject: soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83400/comment/d18f4ce3_baf70fd7?us… :
PS1, Line 10: , and
> Maybe ". These' to avoid a run-on sentience.
Done
https://review.coreboot.org/c/coreboot/+/83400/comment/208ff952_b22ffe0f?us… :
PS1, Line 12: if
> and
Done
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Change subject: soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds
......................................................................
soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds
The APOB NV size/base are embedded into the amdfw binary and read by
the PSP. These need to be synchronized with the FMAP region used by
coreboot to store the APOB data. soc_update_apob_cache() will only
use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the
NV base passed to the PSP needs to reflect that as well.
This fixes the issue of RAM training running on every boot on
non-vboot builds for Myst boards.
TEST=untested, but same change as made for Mendocino
Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/soc/amd/phoenix/Makefile.mk
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/83401/2
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Change subject: soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds
......................................................................
soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds
The APOB NV size/base are embedded into the amdfw binary and read by
the PSP. These need to be synchronized with the FMAP region used by
coreboot to store the APOB data. soc_update_apob_cache() will only
use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the
NV base passed to the PSP needs to reflect that as well.
This fixes the issue of RAM training running on every boot on
non-vboot builds for Skyrim boards.
TEST=build/boot Skyrim (Frostflow), verify RAM training only
run on first boot after flashing.
Change-Id: I9be1699d675331b46ee9c42570700c2b72588025
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/soc/amd/mendocino/Makefile.mk
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/83400/2
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Change subject: sconfig: Provide simple constants for aliased devices
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83400/comment/cb31ee34_c2d44fab?us… :
PS1, Line 10: , and
Maybe ". These' to avoid a run-on sentience.
https://review.coreboot.org/c/coreboot/+/83400/comment/dca1c7c2_de5d3f57?us… :
PS1, Line 12: if
and
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Change subject: Makefile: Finish switch to Makefile.mak from .inc
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
It looks like this is still left to do.
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