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Change subject: nb/via/cx700: Add south module devices to chipset.cb
......................................................................
Patch Set 2:
(1 comment)
File src/northbridge/via/cx700/chipset.cb:
https://review.coreboot.org/c/coreboot/+/82767/comment/f71e4a3b_e1b5d190?us… :
PS1, Line 21: device pci 01.0 alias hda off end
> Is this always the case by design?
Yes, this is all integrated. Datasheet also lists HDA for all variants (CX700/-M/-M2).
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Change subject: cpu/via: Implement cache as RAM
......................................................................
Patch Set 2:
(1 comment)
File src/cpu/via/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/82766/comment/ddb8b756_12f6b3e8?us… :
PS1, Line 111: /* TODO: Or also enable fixed MTRRs? Bug in the code? */
> Does this need to be investigated?
Probably not. Took me a moment to understand that this is a comment to the
comment (I just copied most of the code from the past).
Given that it used to work, works, and enabling empty, fixed MTRRs shouldn't
change a thing, I'll just drop it.
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Change subject: ec/google/chromeec: Stop checking CBI for UCSI
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83252/comment/31651453_360d8053?us… :
PS1, Line 9: Use only EC_FEATURE_UCSI_PPM to determine whether UCSI is enabled.
> Thank you. Please update the commit message, as they have to be self-contained.
Done
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Change subject: via: Start template for VIA C7 w/ CX700 northbridge
......................................................................
Patch Set 2:
(2 comments)
File src/northbridge/via/cx700/clock.c:
https://review.coreboot.org/c/coreboot/+/82765/comment/3412bf3e_0c354848?us… :
PS1, Line 20: default:
> I see a few more cases in `PM_CX700_202.pdf` (System Programming Manual): https://i.imgur. […]
They are not officially supported. I guess it won't hurt much to add them, though.
Originally I was in a do-only-exactly-what-is-needed mood, to see how a less
bloated coreboot would look like. I've a better case in the queue for that though
:D
File src/northbridge/via/cx700/clock.c:
https://review.coreboot.org/c/coreboot/+/82765/comment/d691b32b_bdb3ea9a?us… :
PS2, Line 26: return 200;
Changed this too, because assuming too high makes delays too long, which
is usually better than too short.
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Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83391?usp=email )
Change subject: mb/via/epia-ex: Turn PCI devices on
......................................................................
mb/via/epia-ex: Turn PCI devices on
Change-Id: I0f9bb63ef42b2535c849dc2a6cbdaf31233a4d36
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/mainboard/via/epia-ex/devicetree.cb
1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/83391/1
diff --git a/src/mainboard/via/epia-ex/devicetree.cb b/src/mainboard/via/epia-ex/devicetree.cb
index 732d024..1d23734 100644
--- a/src/mainboard/via/epia-ex/devicetree.cb
+++ b/src/mainboard/via/epia-ex/devicetree.cb
@@ -9,6 +9,19 @@
}"
end
+ device ref ata on end
+ device ref uhci0 on end
+ device ref uhci1 on end
+ device ref uhci2 on end
+ device ref ehci on end
+ device ref pcie on
+ device ref hda on end
+ end
+ device ref south_pci on
+ device pci 08.0 alias ethernet on end
+ device pci 09.0 alias firewire on end
+ end
+
end
end
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Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: via: Start template for VIA C7 w/ CX700 northbridge
......................................................................
via: Start template for VIA C7 w/ CX700 northbridge
The first steps to bring C7 and CX700 support back mainline. Most is
skeleton copied from the `min86' example.
The romstage entry is placed in the northbridge code, as that's where
we'll perform raminit. Support to read the FSB frequency is added right
away, same for a reset function (using CF9 reset), as both are required
for a minimal build test.
A mainboard VIA EPIA-EX is also introduced for build testing, and in
later stages boot testing as well.
Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/cpu/Makefile.mk
A src/cpu/via/Kconfig
A src/cpu/via/Makefile.mk
A src/cpu/via/c7/Kconfig
A src/cpu/via/c7/Makefile.mk
A src/cpu/via/car/cache_as_ram.S
A src/cpu/via/car/exit_car.S
A src/mainboard/via/Kconfig
A src/mainboard/via/Kconfig.name
A src/mainboard/via/epia-ex/Kconfig
A src/mainboard/via/epia-ex/Kconfig.name
A src/mainboard/via/epia-ex/board_info.txt
A src/mainboard/via/epia-ex/devicetree.cb
A src/northbridge/via/cx700/Kconfig
A src/northbridge/via/cx700/Makefile.mk
A src/northbridge/via/cx700/chip.c
A src/northbridge/via/cx700/chipset.cb
A src/northbridge/via/cx700/clock.c
A src/northbridge/via/cx700/reset.c
A src/northbridge/via/cx700/romstage.c
20 files changed, 207 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/82765/2
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Change subject: cpu/via: Implement cache as RAM
......................................................................
cpu/via: Implement cache as RAM
The overall procedure is taken from the original code that was removed
in commit 4c38ed3c38ac (cpu/via/nano: Drop support). Boilerplate at the
start and end was updated (expect timestamp and BIST result in `xmm*'
registers), stack is aligned to 16B, and linker symbols are now used
for the CAR and cached XIP ranges.
Change-Id: Ia190a3006fe897861b7b8a64d47e588871120dd1
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/cpu/via/c7/Kconfig
M src/cpu/via/car/cache_as_ram.S
2 files changed, 161 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/82766/2
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I'd like you to reexamine a change. Please visit
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The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: nb/via/cx700: Add south module devices to chipset.cb
......................................................................
nb/via/cx700: Add south module devices to chipset.cb
Change-Id: Ibd7a7b8c9e1461fa665bb72082489b9a48da63c3
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/northbridge/via/cx700/chipset.cb
1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/82767/2
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