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Change subject: nb/via/cx700: Add south module devices to chipset.cb
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/northbridge/via/cx700/chipset.cb:
https://review.coreboot.org/c/coreboot/+/82767/comment/4556cb67_19b61e13?us… :
PS1, Line 21: device pci 01.0 alias hda off end
Is this always the case by design?
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Change subject: cpu/via: Implement cache as RAM
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Patch Set 1: Code-Review+1
(1 comment)
File src/cpu/via/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/82766/comment/dcb47056_29b1c3a2?us… :
PS1, Line 111: /* TODO: Or also enable fixed MTRRs? Bug in the code? */
Does this need to be investigated?
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: sb/intel/smbus: Implement smbus_send_byte()
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82763/comment/dc8bfb92_3d170bac?us… :
PS1, Line 8:
Was this tested?
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Change subject: console/i2c_smbus: Allow to send data w/o register offset
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Patch Set 1: Code-Review+2
(1 comment)
File src/console/Kconfig:
https://review.coreboot.org/c/coreboot/+/82762/comment/5a4c588e_6f8dd981?us… :
PS1, Line 322: bool "Write to a specific data register"
nit:
```suggestion
bool "Write logs to a specific data register"
```
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Change subject: console: Fix I2C/SMBus console if it's the only slow one
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Patch Set 1: Code-Review+2
(1 comment)
File src/include/console/console.h:
https://review.coreboot.org/c/coreboot/+/82761/comment/2add3212_321813f5?us… :
PS1, Line 72: #define HAS_ONLY_FAST_CONSOLES !(CONFIG(SPKMODEM) || CONFIG(CONSOLE_QEMU_DEBUGCON) || \
: CONFIG(CONSOLE_SERIAL) || CONFIG(CONSOLE_NE2K) || CONFIG(CONSOLE_USB) || \
: CONFIG(EM100PRO_SPI_CONSOLE) || CONFIG(CONSOLE_SPI_FLASH) || \
: CONFIG(CONSOLE_SYSTEM76_EC) || CONFIG(CONSOLE_AMD_SIMNOW) || \
: CONFIG(CONSOLE_I2C_SMBUS))
Would it make sense to replace this with a new `HAVE_SLOW_CONSOLE` Kconfig option (or something with a better name), selected by the relevant consoles?
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Change subject: include/commonlib/sot.h: Add SOT structs
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Patch Set 14:
(1 comment)
File src/commonlib/include/commonlib/sot.h:
https://review.coreboot.org/c/coreboot/+/77882/comment/db72a885_d905e2b6?us… :
PS13, Line 7: <commonlib/bsd/compiler.h>
> Acknowledged
sorry to be late on this
`git grep 'compiler.h' $(find -type f -name "Makefile.*")`
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Change subject: sconfig: Provide simple constants for aliased devices
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS2:
> Hi Subrata, with some required changes in MB fatcat, i am able to boot the bootblock stage.
> Changes done:
> 1. rename config variable to "struct soc_intel_pantherlake_config *config" in file:fatcat/mainboard.c
> 2. rename DT soc var from "chip soc/intel/meteorlake" to "chip soc/intel/pantherlake"
> 3. rename config variable to "struct soc_intel_pantherlake_config *config" in file: fatcat/variants/baseboard/include/baseboard/variants.h
> 4. Add "SOC_INTEL_PANTHERLAKE" and remove mtl specific config such as "SOC_INTEL_METEORLAKE_U_H", "SOC_INTEL_IOE_DIE_SUPPORT" in file: fatcat/Kconfig
> "
sounds good. please share the required code change as well.
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